Dual damascene structure for the wiring-line structures of...

Details Dual damascene structure for the wiring-line structures of... Dual damascene structure for the wiring-line structures of...

2008-05-27

2008-05-27

Pham, Hoai V (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C257S760000, C257SE23145

Reexamination Certificate

active

07378740

ABSTRACT:
An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

REFERENCES:
patent: 5679606 (1997-10-01), Wang et al.
patent: 6245662 (2001-06-01), Naik et al.
patent: 6265780 (2001-07-01), Yew et al.
patent: 6291334 (2001-09-01), Somekh

Affiliated with

Also associated with

Rating

Dual damascene structure for the wiring-line structures of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual damascene structure for the wiring-line structures of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene structure for the wiring-line structures of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2801444