Dual damascene processing method

Details Dual damascene processing method Dual damascene processing method

1997-12-16

1999-12-14

Beck, Shrive

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427509, 427510, 427585, 427588, 427154, 427255, 427259, B05D 512

Patent

active

060014148

ABSTRACT:
A dual damascene processing method comprising the steps depositing sequentially a first oxide layer, a SRO layer and a second oxide layer over a substrate. Then, photolithographic and etching operations are conducted to form a via that links up with a desired wire-connecting region above the substrate. Next, another photolithographic and etching operations are conducted to form interconnect trench lines followed by the deposition of metal into the via and trench. Finally, the surface is polished with a chemical-mechanical polishing operation to remove the unwanted metal on the surface. The invention is capable of controlling the depth of trench and obtaining a smoother trench bottom for the metal lines. Furthermore, the separation of via and trench etching steps makes the control of the final etch profile much easier, thereby able to get an optimal result.

REFERENCES:
patent: 5382545 (1995-01-01), Hong
patent: 5596230 (1997-01-01), Hong
patent: 5635423 (1997-06-01), Huang et al.
patent: 5705430 (1998-01-01), Avanzino et al.
patent: 5731242 (1998-03-01), Parat et al.
patent: 5753967 (1998-05-01), Lin
patent: 5818110 (1998-10-01), Cronin

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