Dual damascene process for capacitance fabrication of DRAM

Details Dual damascene process for capacitance fabrication of DRAM Dual damascene process for capacitance fabrication of DRAM

1999-06-29

2001-01-16

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S255000, C438S398000, C438S725000

Reexamination Certificate

active

06174781

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106625, filed Apr. 26, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device. More particularly, the present invention relates to a fabrication method of a capacitor for a dynamic random access memory (DRAM) cell.
2. Description of the Related Art
According to the conventional manufacturing method of a DRAM capacitor, a first insulation layer is formed on a substrate that contains at least a transistor, followed by the formation of a first node contact plug and a bit line. A second insulation layer is further formed and is defined to form a first opening, exposing the note contact plug. A node plug is formed by filling the first opening with a conductive material. After which, a third insulation layer is formed, centering at the first opening, and is defined to form a second opening with a diameter greater than the first opening. A layer of doped polysilicon is deposited on the bottom and the sidewall of the second opening to form a bottom electrode of a capacitor. Finally, a dielectric layer and a top electrode on the bottom electrode are sequentially formed to complete the manufacturing process of a capacitor.
The node plug and the bottom electrode are conventionally formed by defining the second and the third insulation layers to form the first and the second openings, followed by a deposition of doped polysilicon. The conventional manufacturing method of a capacitor involves multiple steps and is complicated.
SUMMARY OF THE INVENTION
This invention provides a fabrication method of a capacitor of a DRAM, and is also applicable for the manufacturing of other semiconductor devices. The current manufacturing method of a DRAM capacitor comprises the following steps. A substrate comprises a transistor consisting of a gate and source/drain regions, and a planarized first insulation layer on the substrate. The first insulation layer comprises a node contact plug, which is electrically connected to one of the source/drain regions on the side of the gate. A second insulation layer is further formed on the substrate and then defined to form a first opening, exposing the top surface of the node contact plug. After which, the first opening is filled with a fluid precursor to form a sacrificial plug. A portion of the second insulation layer surrounding the sacrificial plug is removed to form a second opening. The bottom of the second opening retains a certain thickness of the second insulation layer. After the removal of the sacrificial plug, a node plug and a first electrode are formed simultaneously in the first opening and on the inner surface of the second opening. Consequently, a dielectric layer is formed on the surface of the first electrode, while a second electrode is formed on the dielectric layer.
According to the current invention, the first electrode and the node plug are formed simultaneously. By using an organic anti-reflecting coating material as the fluid precursor, the sacrificial plug is formed and the bottom anti-reflection layer of the second insulation layer is defined simultaneously. This invention thus comprises at least the advantages of simplifying the manufacturing steps and increasing the productivity.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5702982 (1997-12-01), Lee et al.
patent: 5759888 (1998-06-01), Wang et al.
patent: 5827766 (1998-10-01), Lou
patent: 5856220 (1999-01-01), Wang et al.
patent: 5956587 (1999-09-01), Chen et al.

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