Dual damascene process and structure with dielectric barrier...

Details Dual damascene process and structure with dielectric barrier... Dual damascene process and structure with dielectric barrier...

2000-09-05

2002-02-19

Picardat, Kevin M. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C257S760000, C257S643000

Reexamination Certificate

active

06348733

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of dual damascene wiring in integrated circuits with particular reference to maximizing conductance of the vias.
BACKGROUND OF THE INVENTION
The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.
The introduction of damascene wiring solved several problems that faced the semiconductor industry as wiring grew ever smaller and more complex. A damascene structure is, by definition, planarized, possible leakage problems due to incomplete coverage of wiring by inter metal dielectrics are eliminated, and rapid diffusers such as copper or silver can be more reliably confined by diffusion barriers.
Referring now to
FIG. 1
we show layer
11
of silicon oxide which covers a partially completed integrated circuit (not shown). Embedded in layer
11
is a layer of metal
12
that fills a trench previously formed in the surface of
11
so that the top surfaces of
11
and
12
are co-planar.
In the standard process for contacting layer
12
through a double damascene structure the next steps are illustrated in FIG.
2
. Silicon nitride layer
13
is deposited over the surfaces of
11
and
12
followed by silicon oxide layer
21
. This, in turn, is followed by a second silicon nitride layer in which a via hole opening has been etched prior to over coating with a second silicon oxide layer
23
. Also seen in the figure is a photoresist pattern
24
which will be used to define the trench that will carry the next layer of damascene wiring.
FIG. 3
illustrates the appearance of the structure after etching where via hole
31
extends all the way down to layer
12
and connects at its upper end to trench
32
which extends through layers
22
and
23
. An important step to complete this structure is the deposition of barrier layer
42
, which can be seen in
FIG. 4
, and which coats the walls of trench
32
as well as the walls of via hole
31
and the exposed upper surface of wiring layer
12
. The trench and via hole are then over filled with copper layer
43
and the surface planarized giving the appearance shown in FIG.
4
. Layer
41
of silicon nitride is the equivalent of layer
13
for this level of wiring.
It is important to note that the thickness of layer
42
is a compromise between providing adequate diffusion resistance and minimal electrical resistance. Although the barrier layer material is electrically conducting, its resistivity is relatively high so it increases resistance between the two levels of wiring (
12
and
43
) both because of contact resistance at the interface to
12
and because it occupies a significant portion of the total cross-section of the via hole, thereby reducing the amount of copper available to contribute to the conductance of the via.
During a routine search of the prior art no references that teach the process or structure of the present invention were encountered. Several references of interest were, however, found. For example, Lin (U.S. Pat. No. 5,753,967) deals with the problem of how to center the stud part of a dual damascene structure relative to the trench part. He teaches a self-aligned technique wherein the trench is first formed then given a coating of dielectric which serves as a hard mask for the formation of the stud opening.
Mu et al. (U.S. Pat. No. 5,612,254) describe formation of a dual damascene structure. First the metal stud portion is fully formed in a first dielectric layer. Then, a second layer of dielectric is deposited and the trench portion is aligned and formed therein. In one embodiment, there is a layer of silicon nitride between the two dielectrics but this does not extend into the stud region.
Ireland (U.S. Pat. No. 5,466,639) describes the procedure, detailed above, that has become the ‘standard’ process for forming a dual damascene structure.
Shoda (U.S. Pat. No. 5,689,140) teaches the use of two different adhesion layers in the stud and trench portions of a damascene structure. As a result, when the trench and stud get filled with metal, growth on the upper (trench) adhesion layer does not begin until growth in the lower (stud) portion is well along. Materials of choice for the first adhesion layer include a metal, silicon, and silicides. For the second adhesion layer, preferred materials include metal nitrides, metal borides, and metals.
SUMMARY OF THE INVENTION
It has been in object of the present invention to provide a process for forming a dual damascene structure.
A further object on the invention has been that said dual damascene structure provide low via hole resistance between wiring levels without sacrificing the effectiveness of the diffusion barrier.
These objects have been achieved by means a structure in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.


REFERENCES:
patent: 5466639 (1995-11-01), Ireland
patent: 5612254 (1997-03-01), Mu et al.
patent: 5689140 (1997-11-01), Shoda
patent: 5753967 (1998-05-01), Lin
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6097093 (2000-08-01), Wu et al.

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