Dual damascene interconnect

Details Dual damascene interconnect Dual damascene interconnect

2000-04-13

2003-03-18

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S763000, C257S774000

Reexamination Certificate

active

06534866

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the fabrication of multi-layer integrated circuits, and more particularly to contact formation in a dual damascene interconnect scheme.
BACKGROUND OF THE INVENTION
There are numerous semiconductor process steps involved in the development of modern day integrated circuits (ICs). From the initial fabrication of silicon substrates to final packaging and testing, integrated circuit manufacturing involves many fabrication steps, including photolithography, doping, etching and thin film deposition. As a result of these processes, integrated circuits are formed of microscopic devices and wiring amid multiple layers.
Contact vias or openings are commonly formed in insulating materials known as interlevel dielectrics (ILDs). The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring at various levels. Damascene processing similarly involves etching trenches in insulating layers in a desired pattern for a wiring layer. These trenches are then filled with conductive material to produce the integrated wires. Where contact vias, extending downwardly from the bottom of the trenches, are simultaneously filled, the process is known as dual damascene.
The integrated wires that interconnect between different active devices should be fabricated of a relatively low resistivity material. Aluminum (Al), for example, has generally prevailed as the material of choice in the development of integrated wires or “runners” because of its low resistivity (~2.7 &mgr;&ohgr;-cm). Other favorable characteristics of aluminum include good adhesion to insulation layers such as silicon oxide surfaces (SiO
2
). Copper demonstrates even lower resistivity, though it introduces its own difficulties in integration.
Ideally, highly conductive metals should be employed not only in lateral runners, but also in vertical contact regions. Contact openings, however, are being developed with higher aspect ratios (A/R), such that aluminum can not adequately fill the contact openings by conventional physical vapor deposition (PVD) sputtering. Imperfect aluminum deposition also results in electromigration at points of inadequate fill, especially in the contact regions where there are generally large current densities. Furthermore, Al—Si contact interfaces are prone to junction spiking resulting in large leakage currents or even electrical shorts.
On the other hand, metals for which chemical vapor deposition (CVD) are well developed, such as tungsten (W) are most often employed for filling contact openings with high aspect ratios. Tungsten (W) exhibits excellent resistance to electromigration effects, hillock formation, and humidity-induced corrosion. Since W can be deposited by means of CVD, it allows much better step coverage that can be obtained by sputter-deposited or evaporated films (e.g., Al films). The downside corollary to depositing W is its relatively high resistivity (~6-15 &mgr;&ohgr;-cm). Moreover, separate plug and wiring formation is less efficient than simultaneous formation using dual damascene process flows.
There is consequently a need for improved methods and structures for integrated circuit interconnects, including contacts or plugs and metal runners.
SUMMARY OF THE INVENTION
These and other needs are satisfied by several aspects of the present invention.
In accordance with one aspect of the invention, an interconnect structure is provided. The interconnect is provided in a dual damascene contact via and an overlying trench, which are in turn formed in insulating material of an integrated circuit.
The contact via is partially filled with tungsten that has a greater thickness over a bottom surface of the contact via than over any surface of the trench. A second metal that is more conductive than tungsten fills an upper portion of the contact via, over the tungsten, and at least partially fills the trench.
In accordance with another aspect of the invention, an integrated circuit, is provided with a generally horizontal metal runner in an upper insulating layer. At least a lower portion of the metal runner includes a metal. A generally vertical contact extends downwardly through a lower insulating layer from the metal runner to a lower conductive element. The contact includes an upper portion of the contact formed of the first metal. The upper portion is integrally formed with the lower portion of the metal runner. A lower portion of the contact includes a less conductive material than the metal. The thickness of this lower portion extends between about one-third and two-thirds of a contact height defined between the lower conductive element and the metal runner.
In accordance with another aspect of the invention, a system that includes an integrated contact plug is provided. The plug has a contact height between a lower surface and an upper surface. The contact plug includes a tungsten layer having a thickness over the lower surface equal to between about one-third and two-thirds of the contact height. An aluminum layer extends from the tungsten layer to the upper surface.
In accordance with another aspect of the invention, an integral metallization structure is provided in an integrated circuit. The structure includes a metal runner with a first metal layer. This first metal layer extends downwardly into an upper portion of an underlying contact. The underlying contact also includes a lower portion formed of a second metal layer that extends from the first metal layer downwardly to a contact landing pad.
In accordance with another aspect of the invention, a method is provided for forming an integrated circuit. The method includes forming a dual damascene structure in insulating material over a semiconductor substrate. This dual damascene structure includes a trench and a contact via that extends from the bottom of the trench to expose a conductive element. A first metal is deposited selectively over the conductive element, relative to insulating surfaces of the dual damascene structure, to partially fill the contact via. The remainder of the contact via is then filled with a second metal, which is more conductive than the first metal.
In accordance with another aspect of the invention, a method is provided for fabricating an integrated circuit interconnect structure. A pattern of dual damascene trenches and contact vias is etched in insulating material. A first metal then preferentially deposits into the contact vias to partially fill the contact vias. A second metal layer is then deposited by physical vapor deposition to fill a remaining portion of the contact vias over the first metal and to at least partially fill the trenches.


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