Dual damascene etching process

Details Dual damascene etching process Dual damascene etching process

2005-11-01

2005-11-01

Zarneke, David (Department: 2891)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S724000, C438S744000, C438S709000, C438S710000, C438S711000, C438S714000, C438S723000

Reexamination Certificate

active

06960535

ABSTRACT:
An etching process yields an optimized formation of via holes through the combination of semiconductor material selection and etchant parameters. Over an interlayer dielectric layer is formed a stop layer having a SiON layer over which is a SiC layer. Selective etching will attack the SiC layer while leaving the SiON layer undisturbed. When etching the via hole, a proportion of about 7:90 O2:CO was observed to yield a superior etch.

REFERENCES:
patent: 6362109 (2002-03-01), Kim et al.
patent: 6372636 (2002-04-01), Chooi et al.
patent: 6448177 (2002-09-01), Morrow et al.
patent: 6479391 (2002-11-01), Morrow et al.
patent: 6607986 (2003-08-01), Seta et al.
patent: 6787474 (2004-09-01), Komada
patent: 6790772 (2004-09-01), Chung et al.
patent: 2002/0182880 (2002-12-01), Zhu et al.
patent: 2003/0164354 (2003-09-01), Hsieh et al.
D. Edelstein et al., “Full Copper Wiring in a Sub-0.25 um CMOS ULSI Technology”, Proc. IEEE IEDM, 1997.
S. Venkatesan et al.; “A High Performance 1.8V, 0.20 um CMOS Technology with Copper Metallization”, Proc. IEEE IEDM, 1997.

Affiliated with

Also associated with

Rating

Dual damascene etching process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual damascene etching process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene etching process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3494036