Dual damascence process

Details Dual damascence process Dual damascence process

1998-03-12

1999-11-23

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438742, H01L 2144

Patent

active

059900156

ABSTRACT:
A dual damascene process can be used to form an interconnect. A first dielectric layer is formed on a semiconductor substrate having a device layer formed thereon. A stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the stop layer. A hard mask layer is formed and patterned on the second dielectric layer so that an opening is formed to expose the second dielectric layer therewithin. The second dielectric layer, the stop layer and a part of the first dielectric layer are etched within the opening by photolithography and etching, so that a contact window is formed. Using the hard mask layer as a hard mask, an etching is performed so that a metal trench penetrating through the second dielectric layer is formed, and the device layer within the contact window is exposed.

REFERENCES:
patent: 5466639 (1995-11-01), Ireland
patent: 5518963 (1996-05-01), Park
patent: 5741626 (1998-04-01), Jain et al.

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