Dual-control ring voltage controlled oscillator

Details Dual-control ring voltage controlled oscillator Dual-control ring voltage controlled oscillator

2001-01-31

2002-05-28

Mis, David (Department: 2817)

Oscillators

Ring oscillators

C331S034000, C331S03600C, C331S17700V, C331S17700V

Reexamination Certificate

active

06396358

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of voltage controlled oscillators, and more particularly, the invention is directed to a dual-control ring voltage controlled oscillator having a frequency range greater than two to one and a method to tune its frequency.
BACKGROUND OF THE INVENTION
A voltage controlled oscillator (VCO) is simply a circuit that generates an oscillating signal at a frequency controlled by a voltage supplied from an external source. VCOs are basic building blocks of many electronic systems especially phase-locked loops and may be found in computer disk drives, wireless electronic equipment such as cellular telephones, and other systems having an oscillation frequency controlled by an applied tuning voltage. One basic design for a VCO is the ring oscillator.
Ring oscillators have a number of delay stages of amplifiers wherein the amount of delay of each stage is controlled by an input voltage or current. The input voltage can be further controlled by varying the capacitance of each stage. The output of the Nth stage is coupled to the input of the first stage. The ring oscillator's frequency is inversely proportional to twice the total delay. Very high frequencies can be obtained with ring oscillators by decreasing the delay and decreasing the number of delay stages, but the oscillators are susceptible to noise and jitter. Ring oscillators, depending on the phase noise requirement, will probably require much less power and area than inductor capacitor (LC) oscillators or the multivibrator oscillators and, as a result, are often used in computer disk drive applications. It is particularly useful to achieve an output frequency range of 2:1 meaning that the output frequency can vary from×hertz to 2×hertz so that simple digital dividers can be used to multiply the total range by any factor. LC tank oscillators, for instance, have a frequency range of only approximately thirty percent. Interpolating delay oscillators achieve a frequency range of only 1.6:1. Thus, in the present designs, achieving a 2:1 frequency range requires greater size and circuit power than is desirable in many applications. Small circuit area, moreover, saves manufacturing costs and less power conserves battery life.
With respect to
FIG. 1
, a conventional phase-locked loop (PLL)
10
is shown. PLLs are a broad category of circuits that lock the frequency and phase of an electronic data stream to a system clock. The PLL comprises conventional elements such as a charge pump
20
and a loop filter
22
. Loop filter
22
comprises a capacitor
24
and a resistor
26
in series to achieve rapid lock-in of the appropriate frequency. The voltage across the loop filter
22
is provided to a voltage-to-frequency set point converter
28
which provides a voltage to the oscillator
30
to generate a signal having a frequency proportional to the input voltage from the voltage-to-frequencesy converter
28
. There are many types of oscillators
30
that can be used in the PLL to generate the system clock, and ring oscillators, multivibrators, and LC tank oscillators are just three types of clock generators for PLLs. The output from the oscillator
30
is a clock signal
34
of a selected frequency which is input to the logic synthesizer
36
. The logic synthesizer
36
monitors the frequency of the clock signal
34
and determines if the frequency is too fast or too slow with respect to a reference clock
38
. The output of the logic synthesizer
36
adjusts the charge pump
20
and the voltage-to-frequency converter
28
accordingly with a frequency correction signal
40
and a phase correction signal
42
, if available. There is, however, a charge-up time of the timing loop capacitor
24
so that after its capacitor
24
charges, the clock frequency
34
changes slightly. A disadvantage of this PLL is the large area required for the charge pump capacitor
24
.
FIG. 2
shows a typical ring voltage controlled oscillator
30
in which a number of delay stages
42
,
44
,
46
drive each other in a ring to achieve oscillation. Load capacitors
52
,
54
,
56
on the output of each delay stage can be varied to tune the ring, as in U.S. Pat. No. 5,191,301 entitled Integrated Differential Voltage Controlled Ring Oscillator to Mullgrav issued Mar. 2, 1993, assigned to the same assignee as this application and herein incorporated by reference in its entirety. The frequency of oscillation can be stated as: F=½[N(T
d
+T
c
)]
−1
where T
d
is the fixed time delay per stage which represents the wiring and parasitic capacitance; T
c
is the capacitor variable time delay per stage; and N is the number of delay stages
42
,
44
,
46
. T
c
varies as the capacitance values of capacitors
52
,
54
,
56
are varies. In this arrangement, large tuning ranges can be achieved with large capacitor variations. In order to get a 2:1 frequency range, T
c
must be equal to T
d
, i.e., for each stage, the fixed time delay must be equal to the variable time delay. As T
c
is increased, however, the fixed delay, T
d
, also increases; thus, to achieve a larger frequency range, a larger capacitance is required generating more circuit area and more input and dissipative power.
FIG. 3
shows a typical delay interpolation tuning ring oscillator
30
. As the control voltage
62
changes, the delay interpolator adds or interpolates the delay from two different delay paths
64
,
66
. If the control voltage
62
chooses more of the N
1
path
66
input, the frequency is increased. If the control voltage
62
chooses more of the N
2
path
64
input, the frequency is decreased. Mathematically, the frequency of oscillation is: F=½[T
d
(KN
1
+(1−K)N
2
)]
−1
where T
d
is the fixed time delay per stage, N
1
is the equivalent number of delay stages for the short path
66
; N
2
is the equivalent number of delay stages for the long path
64
; and K is an interpolation variable. As an example, if N
1
=3 and N
2
=5, and K varies between 0 to 1 based on the control voltage, the oscillation frequency varies by a factor of 5/3. Theoretically, however, the total frequency range cannot vary by more than 1.6:1 for a single interpolation stage. In order to achieve a greater than 2:1 frequency range, the delay interpolation circuit can be cascaded. The disadvantage of cascading, however, is increased circuit size and power.
Thus, each of the techniques above require more circuit elements and more power to achieve a greater frequency range. There remains a need in the industry to achieve a frequency ratio greater than 2:1 while minimizing the area required and the circuit power. There is a further need in the industry to simplify a method to maintain constant fine tune frequency control gain of ring VCOs.
SUMMARY OF THE INVENTION
These needs and other are met by an embodiment of the present invention, herein disclosed as a dual-control ring voltage controlled oscillator, comprising a delay interpolator connected to at least a short path and a long path; each of the paths having a plurality of delay stages at the output of the delay interpolator with the short path having fewer delay stages than the long path; a plurality of variable capacitors interspersed among the plurality of delay stages; an input coarse tune code to vary the capacitance of the plurality of variable capacitors; and an input fine tune code to vary an interpolation variable thereby interpolating the delay through the short path and/or long path. The dual control ring voltage controlled oscillator has an output frequency range of at least two to one.
The dual-control ring voltage controlled oscillator may further comprise a coarse tune digital-to-analog converter to generate a coarse tune current input into the delay interpolator in response to the coarse tune code; and a fine tune digital-to-analog converter to generate a fine tune current input into the delay interpolator in response to the fine tune code; the sum of the coarse tune curren

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