Dual clocking scheme in a multi-port RAM

Details Dual clocking scheme in a multi-port RAM Dual clocking scheme in a multi-port RAM

1998-02-17

1999-09-28

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36523005, 36518905, 36523008, G11C 800

Patent

active

059599375

ABSTRACT:
A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.

REFERENCES:
patent: 5566318 (1996-10-01), Joseph
patent: 5812490 (1998-09-01), Tsukude
patent: 5815462 (1998-09-01), Konishi et al.

Affiliated with

Also associated with

Rating

Dual clocking scheme in a multi-port RAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual clocking scheme in a multi-port RAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual clocking scheme in a multi-port RAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-711520