Dual-clock edge triggered flip-flop circuits

Details Dual-clock edge triggered flip-flop circuits Dual-clock edge triggered flip-flop circuits

1984-03-14

1986-08-19

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307289, H03K 3037

Patent

active

046071733

ABSTRACT:
A dual-clock, edge triggered, flip-flop circuit wherein one set of outputs responds to two independent inputs without giving rise to indeterminate states regardless of the combination of inputs comprising a first pair of gates (1-2 or 11-12) cross-coupled to form a first trigger flip-flop. A second pair of gates (7-8 or 17-18) are cross-coupled to form a second trigger flip-flop. A third pair of gates (4-5 or 14-15) are cross-coupled to form an output flip-flop having set and reset terminals and a pair of output terminals. A gate (3 or 13) is coupled from the output of the first trigger flip-flop to the set terminal of the output flip-flop, the input to the first trigger flip-flop also being coupled to the input of this latter gate. Another gate (6 or 16) is coupled from the output of the second trigger flip-flop to the reset terminal of the output flip-flop, the input to the second trigger flip-flop also being coupled to the input of this gate. Each output terminal is cross-coupled back to the input of a respective one of the trigger flip-flops to "disarm", or reset, the same after the output flip-flop has changed state.

REFERENCES:
patent: 3467839 (1969-09-01), Miller
patent: 3967206 (1976-06-01), Roberson et al.
patent: 3989960 (1976-11-01), Kodama
patent: 4072869 (1978-02-01), Gillow
Kershaw, John D., Digital Electronics: Logic and Systems, Duxbury Press, (1976, p. 197).
"TTL Data Book," Fairchild Semiconductor, Inc., pp. 4-144 and 145.

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