Dual clock domain interface between CPU and memory bus

Details Dual clock domain interface between CPU and memory bus Dual clock domain interface between CPU and memory bus

1992-07-29

1995-09-05

Heckler, Thomas M.

G06F 108

Patent

active

054487153

ABSTRACT:
A system and method for isolating the timing domain of a central processing unit (CPU) from the timing domain of a memory bus is described. The CPU interfaces with memory and input/output through a dual clock domain interface (DCDI). The DCDI allows the CPU and memory to operate at frequency ratios of N:M, where N and M are positive integers, with N greater than or equal to M. The CPU operating clock speed is not constrained by the operating speed of the memory and input/output. The primary components of the DCDI are: 1) domain translation buffers, 2) clock control circuit, 3) output data queue and 4) receiver modifier circuits. A domain translation buffer takes data from one clock domain and translates it into another clock domain. The clock control circuit generates appropriate clocks according to the current frequency ratio of the system. An output data queue is required when the CPU generates data faster than the memory can accept. A receiver modifier circuit fills in empty states with appropriate signal values for each of the memory bus protocol lines during memory to CPU transfers.

REFERENCES:
patent: 4527145 (1995-07-01), Haussmann et al.
patent: 5099477 (1992-03-01), Taniguchi et al.

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