Dual-chip packaging

Details Dual-chip packaging Dual-chip packaging

1999-12-22

2002-02-05

Easthom, Karl D. (Department: 2832)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S735000, C257S780000

Reexamination Certificate

active

06344687

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a manufacturing process and structure of a dualchip package. More particularly, the present invention relates to a dual-chip package in which metal studs and solder balls are employed as connection media to external circuitry.
2. Description of Related Art
High performance, high level of integration, low cost, increased miniaturization of components and devices are all the common goals in the semiconductor design and manufacture. Mass production of 0.18 microns semiconductor devices are currently achieved and its integration level need not be emphasized. However, higher carrier density, smaller in overall volume, etc. are still main concerns for having high integration level of electronic packaging. Indeed, no matter whether on computers or general commodities, in order to reduce the overall size and the cost, a technique of putting two or more individual chips in a single package has been developed. This kind of packaging will be mainstream in the future. Multichip packaging can be employed to integrate processors and memory chips, or Logic chips and memory chips (including DRAMs, Flash memories, etc.) in a single package. Thus, the cost and the overall size are reduced. Moreover, signal transmission distances can be shortened, and hence, the performance is enhanced. In addition, different individual chips with different fabrication processes can be put together in a single package and no special integration manufacturing processes is required.
Reference is made to
FIG. 1
, which illustrates a prior art dual-chip packaging structure. This kind of structure has been disclosed in Japanese Laid-Open Utility Model Application No. 147360/1978 (Jitsukaisho 62-147360). Two chips
100
,
102
are attached to two surfaces of a die pad
104
, respectively, and connected to conductive leads
106
through bonding wires
108
. An encapsulant is employed to enclose the two chips
100
and
102
, inner portions of the conductive leads
106
, and the bonding wires
108
. However, a conventional leadframe is employed as a carrier in this dual-chip packaging structure, so the level of integration is limited and signal paths are relatively longer. Moreover, after a first chip is attached on the die pad and wire bonding is completed, a special clamping apparatus is required for attaching a second chip on the die pad and wire bonding operation. Thus, both the cost and the manufacturing complexity are increased.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a dual-chip packaging structure having a relatively high level of integration and short signal paths
Another object of the present invention is to provide a dual-chip packaging structure having a relatively small overall packaging volume.
Yet another object of the present invention is to provide a dual-chip packaging structure having simple manufacturing process and low cost of production.
To achieve these objects and other advantages and in accordance with the present invention, a dual-chip packaging structure is described herein, which comprises a die pad, to each of whose two surfaces is respectively attached a chip. Outside and around the die pad is a plurality of first metal studs. A plurality of second metal studs is arranged outside and around the first metal studs. Connections between the first metal studs and the second metal studs are made by means of a plurality of conductive traces. The two chips on respective surfaces of the die pad are connected to corresponding ends of the first metal studs through bonding wires. An insulating material is employed to enclose the two chips, the die pad, the first metal studs, the conductive traces, and ends of the second metal studs, with other ends of the second metal studs exposed. A plurality of solder balls is attached to the respective exposed ends of the second metal studs.
To achieve these objects and other advantages and in accordance with the present invention, a manufacturing process for a dual-chip packaging structure is described herein, which comprises a conductive substrate having a first surface, a second surface, and a die pad region. Outside and around the die pad region is a plurality of first metal stud regions. A plurality of second metal stud regions is arranged outside and around the first metal stud regions. Connections between the first metal stud regions and the second metal stud regions are made by means of a plurality of conductive trace regions. A mask layer is formed which covers the second surface, the die pad of the first surface, the first metal stud regions, the second metal stud regions, and the conductive trace regions. The first surface is then half etched such that the uncovered portions of the first surface are removed and a predetermined thickness is obtained. A first chip is attached on the die pad region of the first surface. Connections between the first chip and the first metal stud regions are made by bonding wires. A first insulating layer is formed which covers the first surface. The second surface is etched until the first insulating layer is exposed. In this instance, a die pad, first metal studs, second metal studs, and conductive traces are formed at the corresponding regions. A second chip is attached to the die pad of the second surface. Connections between the second chip and the first metal studs are made by the conductive traces. A second insulating layer is formed which covers the second surface with portions of the second metal studs of the second surface exposed. A plurality of solder balls is attached to the exposed portions of the second metal studs of the second surface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5545922 (1996-08-01), Golwalkar et al.
patent: 5596225 (1997-01-01), Mathew et al.
patent: 5818102 (1998-10-01), Rostoker
patent: 5889325 (1999-03-01), Uchida et al.
patent: 5905639 (1999-05-01), Warren
patent: 6153928 (2000-11-01), Cho

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