Dual-chip integrated circuit package and method of...

Details Dual-chip integrated circuit package and method of... Dual-chip integrated circuit package and method of...

1999-12-22

2003-07-08

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S670000, C257S690000, C257S678000, C257S777000, C257S686000, C257S787000, C257S784000

Reexamination Certificate

active

06590279

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package.
2. Description of Related Art
An integrated circuit package is typically formed with a single semiconductor chip. To allow increased functionality and density of electronic components from a single integrated circuit package, it is usually desired and a tendency to pack two or more semiconductor chips rather than just one in an integrated circuit package. An integrated circuit package that packs two integrated circuit chips therein is customarily referred to as a dual-chip integrated circuit package.
The U.S. Pat. No. 5,793,108 discloses a dual-chip integrated circuit package.
FIG. 8
is a schematic sectional diagram showing the structure of this dual-chip integrated circuit package. As shown, this dual-chip integrated circuit package includes a leadframe
100
having a die pad
101
for mounting a first integrated circuit chip
120
and a second integrated circuit chip
140
. The first integrated circuit chip
120
has its front side
121
attached to the die pad
101
by means of an insulative film
110
. The bonding pads
123
on the first integrated circuit chip
120
are electrically connected via a plurality of gold wires
150
to the first surface
102
a
of the leads
102
of the leadframe
100
. An insulative adhesive layer
130
is then coated on the back side
122
of the first integrated circuit chip
120
for attaching the first integrated circuit chip
120
to the back side
142
of the second integrated circuit chip
140
. The bonding pads
143
on the front side
141
of the second integrated circuit chip
140
are electrically connected via a plurality of gold wires
160
to a second surface
102
b
of the leads
102
. Further, an encapsulant
170
is formed to encapsulate the first integrated circuit chip
120
, the second integrated circuit chip
140
, and the inner part of the leads
102
. Active circuitry is formed on the front side
121
of the first integrated circuit chip
120
and the front side
141
of the second integrated circuit chip
140
.
The forgoing dual-chip integrated circuit package, however, has the following drawbacks. First, it requires the bonding pads
123
on the front side
121
of the first integrated circuit chip
120
to be exposed out of the die pad
101
so as to facilitate the connection of the bonding pads
123
with the gold wires
150
. This requires the jointed area between the first integrated circuit chip
120
and the die pad
101
to be smaller than the area of the front side
121
of the first integrated circuit chip
120
. However, after the second integrated circuit chip
140
has been attached to the first integrated circuit chip
120
, the beneath of the bonding pads
143
on the second integrated circuit chip
140
is a void space without support from the die pad
101
. As a consequence, as shown in
FIG. 9
, during the wire bonding process to connect the bonding wires
160
, the second integrated circuit chip
140
is only partly supported by the fixture
180
positioned underneath the die pad
101
, which would easily cause the areas near the bonding pads
143
on the second integrated circuit chip
140
and the bonding pads
123
on the first integrated circuit chip
120
to be cracked. Second, since the front side
121
of the first integrated circuit chip
120
is attached to the die pad
101
in a direct face-to-face manner, the first integrated circuit chip
120
could easily subjected to delamination during any temperature change in the manufacture process. This is because that the first integrated circuit chip
120
differs in coefficient of thermal expansion from the die pad
101
. The direct face-to-face attachment also requires the insulative film
110
to be large enough to cover the whole of the die pad
101
. This practice, however, would considerably increase the manufacture cost. Moreover, the insulative film
110
being made large would hamper the drainage of the air between the insulative tape
110
and the die pad
101
and the air between the insulative tape
110
and the first integrated circuit chip
120
, which would undesirably cause voids to be formed in these parts. Under a subsequent high-temperature process condition, the existence of such voids would cause a popcorn effect, which could damage the integrated circuit package structure. Still one drawback is that when the foregoing dual-chip integrated circuit package is made into a low profile device, the gap between the bottom side of the die pad
101
and the bottom of a cavity of an encapsulation mold (not shown) would become very small, causing the flow of the melted molding compound to be slowed down, resulting in the undesired forming of voids in the formed encapsulant. The forming of these voids could also lead to the problem of a popcorn effect.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a dual-chip integrated circuit package, which can help prevent the chips from being cracked during the manufacture process.
It is another objective of this invention to provide a dual-chip integrated circuit package, which can help prevent delamination from occurrence during the manufacture process.
It is still another objective of this invention to provide a dual-chip integrated circuit package, which can help prevent the occurrence of voids in the encapsulant.
In accordance with the foregoing and other objectives, the invention proposes a new dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package.
The dual-chip integrated circuit package of the invention includes: (a) a first integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; (b) a second integrated circuit chip having a front side and a back side, with the front side being formed a plurality of bonding pads; the second integrated circuit chip being attached to the first integrated circuit chip in a back-to-back manner; (c) a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads; at least one support member attached to the front side of the first integrated circuit chip being for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located; (d) a plurality of bonding wires for connecting the bonding pads on the first integrated circuit chip to the first leads and the bonding pads on the second integrated circuit chip to the second leads; (e) at least one insulative adhesive for attaching the support member to the front side of the first integrated circuit chip; and (f) an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe.
The method according to the invention for manufacturing the foregoing dual-chip integrated circuit package includes the following steps: (1) preparing a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads; (2) mounting a first integrated circuit chip onto the support members of the leadframe, the first integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; the first integrated circuit chip being mounted onto the support members in such a manner that the front side thereof faces the support members and the bonding pads on the first integrated circuit chip are separated from any of the support members; (3) performing a first wire-bonding process to connect a plurality of bonding wires between the bonding pads

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