Dual channel FIFO circuit with a single ported SRAM

Details Dual channel FIFO circuit with a single ported SRAM Dual channel FIFO circuit with a single ported SRAM

1996-03-22

1998-04-28

Barry, Lance Leonard

395431, 395877, G06F 1300

Patent

active

057457310

ABSTRACT:
In accordance with the present invention, there is provided a dual channel FIFO circuit to perform bidirectional data transfer under the control of a host computer between a host interface and a small computer system interface, comprising: a first multiplexing means for selecting one of the data from said host interface and the data from said small computer system interface; a single ported SRAM for storing the selected data by said first multiplexing means and outputting the data, which are indicated by pointers, according to the requests from said host interface or said small computer system interface; a second multiplexing means for selecting one of the data from said single ported SRAM and the data from said small computer system interface; a first staging memory means for storing the data to be outputted to said host interface; and a second staging memory means for storing the selected data by said second multiplexing means and transferring them to said second multiplexing means and said small computer system interface.

REFERENCES:
patent: 4899352 (1990-02-01), Cucchi et al.
patent: 4949301 (1990-08-01), Joshi et al.
patent: 5305319 (1994-04-01), Sowell
patent: 5343435 (1994-08-01), Bourekas et al.
patent: 5495451 (1996-02-01), Cho
patent: 5546347 (1996-08-01), Ko et al.
patent: 5568443 (1996-10-01), Dixon et al.

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