Dual channel clock recovery circuit

Details Dual channel clock recovery circuit Dual channel clock recovery circuit

1982-08-16

1990-11-06

Cangialosi, Salvatore

Pulse or digital communications

Repeaters

Testing

380 6, 375113, 375120, H04K 100

Patent

active

049691600

ABSTRACT:
Apparatus is provided for detecting the presence of a periodically keyed random modulated signal source. Received signals are stepped down to an intermediate frequency and then applied to pairs of narrow bandpass filters. The output from pairs of the narrow bandpass filters are applied to mixers to provide difference frequency signals occurring at the clock rate of the periodically keyed random modulated signal. The clock signal is processed through recovery circuits including a detector and a comparator A signal is generated at the output of the comparator when the clock signal is detected above the background noise and interference, thus, indicating the presence of a periodically keyed random modulated signal source.

REFERENCES:
patent: 3959601 (1976-05-01), Olevsky et al.
patent: 4339824 (1982-07-01), Tanimoto
patent: 4375693 (1983-03-01), Kuhn
patent: 4375694 (1983-03-01), Kuhn
patent: 4472817 (1984-09-01), Poklemba et al.
patent: 4475208 (1984-10-01), Ricketts

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