Dual cell memory device having a top dielectric stack

Details Dual cell memory device having a top dielectric stack Dual cell memory device having a top dielectric stack

2005-05-17

2005-05-17

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185290

Reexamination Certificate

active

06894932

ABSTRACT:
A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A bottom dielectric layer is formed over the substrate and a charge trapping dielectric layer is formed over the bottom dielectric layer. A multi-layer top dielectric stack is formed over the charge trapping dielectric layer. The top dielectric stack includes a first oxide layer, a nitride layer, and a second oxide layer. A wordline is formed over the top dielectric stack. The multi-layer top dielectric stack has a reduced electrical thickness, thereby providing a memory device, which is operative to be programmed using a reduced operating voltage of less than about +8 Volts.

REFERENCES:
patent: 6690601 (2004-02-01), Yeh et al.

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