Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
1999-04-30
2001-07-31
Kinkead, Arnold (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S143000, C102S215000, C102S218000, C361S251000, C307S141400
Reexamination Certificate
active
06268775
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to electronic delay detonators and, in particular, to programmable electronic initiation delay detonators.
Electronic detonators are known for use in initiating explosive charges, e.g., for initiating booster charges used in mining and excavation applications. Such detonators are known for their precise delay characteristics relative to more traditional chemical-based delay units.
2. Related Art
U.S. Pat. No. 5,377,592 to Rode et al, dated Jan. 3, 1995, discloses an electronic digital delay unit powered by a pulse of energy generated by a piezoelectric transducer in response to an impulse-type initiation signal. The initiation signal stimulates the piezoelectric transducer to create a charge of electrical energy that is stored in a storage capacitor. Energy is drawn from the storage capacitor to run a timer circuit comprising an oscillator and a counter that counts oscillation pulses from the oscillator to a predetermined count. When the predetermined count is reached, a signal is generated to discharge the remaining energy from the storage capacitor to the electric igniter element, e.g., an exploding bridgewire. The detonator may be equipped with an externally accessible programming interface so that the timer circuit may be programmed with a delay after the detonator is constructed.
U.S. Pat. No. 5,435,248 to Rode et al, dated Jul. 25, 1995, discloses an electronic range digital delay detonator comprising fusible links that are used to perrnanently program a desired function delay into the detonator circuit.
Electronic detonators of the type described in aforesaid U.S. Pat. No. 5,435,248 and U.S. Pat. No. 5,377,592 comprise conventional oscillators and counters.
SUMMARY OF THE INVENTION
The present invention provides several novel features that find utility in electronic delay detonators. One feature of the present invention relates to an oscillator circuit for generating a clock signal comprising a series of clock pulses. The oscillator circuit comprises a reference voltage means for producing a reference voltage. There are at least two capacitors in the oscillator, each capacitor having one of a charged state and a discharged state relative to the reference voltage. A capacitor in the discharged state has a voltage less than the reference voltage and is designated a discharged capacitor, and a capacitor in the charged state has a voltage that exceeds the reference voltage and is designated a charged capacitor. There is a charging means for charging a discharged capacitor to a charged state and a discharging means for discharging a charged capacitor, designated a charged working capacitor, to a discharged state. The oscillator further comprises a comparator for generating an internal signal each time a charged working capacitor becomes a discharged capacitor. There is a switching means for performing a switching function comprising effectively disconnecting a discharged capacitor from the discharging means and connecting it to the charging means, and for effectively disconnecting a charged capacitor from the charging means and connecting it to the discharging means, and a latch for issuing a clock pulse in response to the internal signals. The switching means may be responsive to the latch, for performing the switching function in response to clock pulses issued by the latch.
The invention also relates to a programmable electronic timer circuit for issuing a timer output signal after the expiration of a programmed time delay following the receipt of an electrical initiation signal. The timer circuit comprises a gated oscillator circuit (optionally as described above) for issuing, in response to a clock enable signal, a clock signal comprising a series of clock pulses, and a resetting circuit for generating a power-on RESET signal. The timer also comprises an initializable ripple counter configured to count clock pulses and to produce the timer output signal when a predetermined count is reached. The ripple counter comprises a plurality of sequential counter stages each capable of having either one of a set state and a clear state and comprising a set input by which the state of the counter stage can be set and a clear input by which the state of the counter stage can be cleared. Each counter stage further comprises at least one output for a counter stage signal that indicates the state of the counter stage. The timer circuit further comprises a program bank comprising both a setting circuit and a clearing circuit associated with each counter stage. Each setting circuit provides a set signal to the set input of the associated counter stage in response to a counter load signal from a control circuit and each clearing circuit provides a signal to the clear input of the counter stage in response to one of a counter load signal and a power-on RESET signal. The clearing circuit produces a signal of finite duration, but the setting circuit is configured to provide a set signal having either of two different finite durations, one of which exceeds the duration of the clearing circuit signal. The associated counter stage can receive signals from the setting circuit and the clearing circuit simultaneously, and the counter stage is configured so that the longer signal determines the initial state of the associated counter stage. The timer circuit further comprises a control circuit which is responsive to a power-on RESET signal and to an electrical initiation signal for issuing the counter load (RST) signal and the clock enable (CLKEN) signal.
According to one aspect of the invention, each setting circuit may comprise a non-volatile program means that can be set to make the setting circuit provide the set signal of longer duration than the clearing circuit signal. Optionally, each setting circuit may comprise a programming input and a data input, wherein the state of the non-volatile program means is determined by the state of the data signal when a programming signal is received at the programming input.
According to another aspect of the invention, the non-volatile program means may comprise an EEPROM cell.
According to still another aspect of the invention, the counter stage outputs may be connected to the data inputs of the associated setting circuits so that each counter stage can provide a data signal for the associated setting circuit.
The present invention also provides a lock-out electronic timer circuit, which may or may not be programmable as described above, for issuing a timer output signal after the expiration of a time delay following the receipt of an electrical initiation signal. This timer circuit comprises an oscillator circuit (optionally as described above) which is responsive to a RESET signal, for issuing at least one reference clock signal comprising a series of reference clock pulses. A ripple counter is configured to count the reference clock pulses and to produce the timer output signal when a predetermined count is reached. There is a clock gate through which the ripple counter receives the reference clock pulses when the clock gate receives a CLKEN signal. There is also a control circuit comprising a control bank comprising three control stages connected in ripple fashion. The three control stages comprise a lock-out control stage, a counter load control stage and a clock enable control stage, and each control stage is capable of having either one of a set state and a clear state and being responsive to a RESET signal that initializes each control stage to the clear state, each control stage having an output that provides a signal indicating the state of the control stage. The control circuit further comprises a enable override circuit for generating a CLKEN signal when the clock enable control stage generates a set signal. The control circuit further comprises a programmable, non-volatile lock-out switch circuit capable of having either one of a set state and a clear state. The lock-out switch circuit is driven to the set state in response to the output signal from the lo
Kinkead Arnold
Libert & Associates
Spaeth Frederick A.
The Ensign-Bickford Company
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