Dual cache memory device with cache monitoring

Details Dual cache memory device with cache monitoring Dual cache memory device with cache monitoring

1992-11-02

1996-02-06

Robertson, David L.

G06F 1300

Patent

active

054902622

ABSTRACT:
A CPU connected to a memory storing module programs has an instruction cache for reading a module header heading a module program and module instructions following the module header out of the memory, and storing and transferring them. An operand cache reads module data included in the module program of interest out of the memory, and stores and transfers them. A processing section performs arithmetic and logical operations in pipelining with the module header of the module program transferred from the instruction cache and with the module data transferred from the operand cache. A pipelined instruction control controls other circuitry of the CPU by decoding the module instructions of the module program transferred from the instuction cache. The CPU transfers the module header to the processing section via the instruction cache while writing the whole block of module header and module instructions to the instruction cache. Alternatively, the CPU may transfer the module header to the processing section via the operand cache while writing the whole block of module header and successive module instructions to the instruction cache.

REFERENCES:
patent: 4777594 (1988-10-01), Jones et al.
patent: 4851993 (1989-07-01), Chen et al.
patent: 4982402 (1991-01-01), Beaven et al.
patent: 4989140 (1991-01-01), Nishimukai et al.
Saburo Kaneda, "Genral Purpose Computer", Trans. of Institute of Electronics Information & Communication Engineers of Japan, vol. 73, No. 4, pp. 344-350, Apr. 1990.

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