Dual cache for independent prefetch and execution units

Details Dual cache for independent prefetch and execution units Dual cache for independent prefetch and execution units

1986-10-16

1987-10-20

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 900

Patent

active

047018445

ABSTRACT:
A pipelined digital computer processor system (10, FIG. 1) is provided comprising an instruction prefetch unit (IPU,2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, FIG. 3) for storing frequently accessed data, and a tag store (82, 92, FIG. 3) for indicating which main memory locations are contained in the respective cache.

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