Dual bus memory controller

Details Dual bus memory controller Dual bus memory controller

2002-03-26

2004-04-06

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S230010, C365S230030, C365S198000, C710S240000, C710S107000

Reexamination Certificate

active

06717834

ABSTRACT:

BACKGROUND
This invention relates to a dual bus memory controller.
A computer system with multiple processors relies on memory to store data and instructions processed and executed by the processors. The processors access the memory by generating memory access requests which are converted by a memory controller into memory access commands that are compatible with the memory. The rate at which the memory controller can process memory access requests may be slower than the rate at which the memory can process the commands. Consequently, the memory controller can adversely affect the rate at which data is exchanged between the memory and the processors.


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