Dual bus dual bank architecture for motion compensation

Details Dual bus dual bank architecture for motion compensation Dual bus dual bank architecture for motion compensation

1993-02-25

1996-01-16

Britton, Howard W.

Television

Bandwidth reduction system

Data rate reduction

348413, 348699, H04N 732

Patent

active

054852145

ABSTRACT:
A memory architecture for use in a video coder comprises two sets of memories and two buses. The memory architecture is used to increase the efficiency of use of a Motion Estimation Unit (MEU) in the video coder.

REFERENCES:
patent: 4897720 (1990-01-01), Wu et al.
patent: 4937666 (1990-06-01), Yang
patent: 5142360 (1992-08-01), Niihara
patent: 5200820 (1993-04-01), Charavi
patent: 5206723 (1993-04-01), Parke
patent: 5210605 (1993-05-01), Zaccarin
L. De Vos et al, "VLSI Architectures for th Full-Search Blockmatching Algorithm", IEEE ICASSP, pp. 1687-1690 (1989).
T. Komarek et al., "Array Architecture for Block Matching Algorithms", IEEE, Trans. on Circ. and Systesm, vol. 36, No. 10, Oct. 1989, pp. 1301-1308.
L. De Vos et al, "Parameterizable VLSI Architecture . . . Algorithm", IEEE Trans. On Cir. and Systems, vol. 36, No. 10, Oct. 1989 pp. 1309-1316.
Kun-Min Yang et al, "A Family of VLSI Designs for the Motion Compensation . . . " IEEE Trans. on Cir. and Systems, vol. 36, No. 10, Oct. 1989, pp. 1317-1325.

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