Dual bus adaptable data path interface system

Details Dual bus adaptable data path interface system Dual bus adaptable data path interface system

1995-03-08

1996-09-03

Harvey, Jack B.

395309, G06F 1342

Patent

active

055532497

ABSTRACT:
A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.

REFERENCES:
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5195089 (1993-03-01), Sindhu et al.
patent: 5404462 (1995-04-01), Datwyler et al.
patent: 5442754 (1995-08-01), Datwyler et al.
patent: 5444860 (1995-08-01), Datwyler et al.

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