Dual buffer video display system for the display of asynchronous

Details Dual buffer video display system for the display of asynchronous Dual buffer video display system for the display of asynchronous

1993-03-26

1995-04-04

Powell, Mark R.

G06F 1520

Patent

active

054044464

ABSTRACT:
A video signal is received from an asynchronous link (15) at an irregular frame rate for display on a computer monitor 9 at a regular frame rate. Frames are transferred to the monitor via first and second buffers (23, 25). A control process (27) manages the transfer of frames between the first and second buffers and is responsible for deciding if, when and how many frames to transfer, in order to minimise the delay between the incoming image and the displayed image.

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IBM Technical Disclosure Bulletin, vol. 10, No. 1, Jun. 1967, pp. 34-36, H. E. Jenkins et al., "Asynchronous Control of Data Transfer".

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