Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device
Reexamination Certificate
2002-01-30
2003-09-30
Elms, Richard (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
C257S315000, C257S316000, C257S319000, C257S320000, C257S326000, C257S314000
Reexamination Certificate
active
06627927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a flash memory cell and its memory array and, more particularly, to a scalable dual-bit memory cell and its memory array for high-density mass storage applications.
2. Description of the Related Art
A stack-gate flash memory cell is known to be a one-transistor cell, in which the gate length of a cell can be defined by using the minimum-feature-size (F) of technology used. Therefore, the stack-gate flash memory cell is often used in existing high-density flash memory system. The stack-gate flash memory cells can be interconnected in series to form a high-density NAND-type array with common source/drain diffusion regions. However, the read speed is slow for an NAND-type array due to the series resistance of the configuration. Moreover, an NAND-type flash memory cell is programmed by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common source/drain diffusion region and its programming speed is relatively slow. In addition, when the gate length of a stack-gate flash memory cell in an NAND-type array is further scaled down, the junction depth of common-source/drain diffusion regions must be scaled accordingly, and the overlapped region between the floating-gate and the common-source/drain diffusion region becomes smaller, resulting in a further slow process for programming and erasing.
The stack-gate flash memory cell can be connected with a common-source diffusion line and each of the drain diffusion regions being connected to a bit line through a contact for an NOR-type flash memory array. The read speed of an NOR-type flash memory array is much faster as compared to that of an NAND-type flash memory array. Moreover, a stack-gate flash memory cell in an NOR-type flash memory array is in general programmed by channel hot-electron injection and its programming speed is much faster than that of an NAND-type flash memory array. The erasing speed of an NOR-type flash memory array is quite similar to that of a NAND-type flash memory array and is limited by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common-source diffusion line.
A typical NOR-type array is shown in
FIG. 1A
, in which FIG.
1
A(
a
) shows a cross-sectional view of an NOR-type flash memory array in A—A′ direction as indicated in FIG.
1
A(
b
) and FIG.
1
A(
b
) shows a top plan view of an NOR-type flash memory array. As shown in FIG.
1
A(
a
) and FIG.
1
A(
b
), a larger active region must be preserved for a contact formed on a heavily-doped (n+) drain diffusion region in order to connect with a bit line (BL) and an unit cell as marked by the dash line is in general equal to or larger than 9F
2
. It is clearly seen that the larger cell size of an NOR-type flash memory array is a major obstacle for high-density mass storage applications. Therefore, a flash memory cell taking advantages of the high-density feature of a stack-gate structure becomes a major trend of technology development and
FIG. 1B
shows one of the examples, in which FIG.
1
B(
a
) shows a cross-sectional view of a dual-bit flash memory cell and FIG.
1
B(
b
) shows a top plan view of the dual-bit flash memory cell.
As shown in FIG.
1
B(
a
) and FIG.
1
B(
b
), a gate region of a dual-bit flash memory cell including two stack-gate transistors
22
G,
20
G and a select-gate transistor
24
G is formed on a semiconductor substrate
26
, in which two common N
+
/N
−
diffusion regions
22
A,
20
A are formed in the semiconductor substrate
26
outside of the gate region and a select-gate line (SG) is formed above two common N
+
/N
−
diffusion regions and two stack-gate transistors, and on a gate-dielectric layer
24
A being formed on a semiconductor substrate
26
. Since the stack-gate transistor, the select-gate transistor and the common N
+
/N
−
diffusion region can be defined by a masking photoresist step with a minimum-feature-size F, the cell size of each bit in a dual-bit flash memory cell is 4F
2
if the select-gate line and its space can be defined to be a minimum-feature-size F. Apparently, there are several drawbacks: very high capacitance between the select-gate line (SG) and the common N
+
/N
−
diffusion regions
22
A,
20
A; very high capacitance between the select-gate line(SG) and the control-gate lines
22
C,
20
A; isolation between the common N
+
/N
−
diffusion regions is poor for the regions outside of the select-gate region
24
A; and isolation between nearby select-gate lines is very poor for the regions under the control-gate lines
22
C,
20
C. It should be noted that poor isolation between nearby select-gate lines may result in an erroneous data reading from nearby cells under the same control-gate line.
It is therefore an objective of the present invention to provide a dual-bit flash memory cell having a cell size of each bit being smaller than 4F
2
and scalable.
It is another objective of the present invention to provide a shallow-trench-isolation structure for the dual-bit flash memory cells in nearby rows of an array.
It is further objective of the present invention to provide two common-source conductive bus lines for a dual-bit flash memory cell in a contactless NOR-type array to enhance the erasing speed.
It is yet another objective of the present invention to provide two common conductive bit lines for a dual-bit flash memory cell with a select-gate in a contactless NOR-type array to enhance the erasing speed.
Other objectives and advantages of the present invention will be more apparent from the following description.
SUMMARY OF THE INVENTION
The dual-bit flash memory cells and their memory arrays are disclosed by the present invention. A dual-bit flash memory cell is formed on a semiconductor substrate of a first conductivity type with an active region being formed between two shallow-trench-isolation (STI) regions and each of STI regions comprises a raised field-oxide layer. The dual-bit flash memory cell of the present invention includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region is formed between the first-side region and the second-side region and is defined by a masking photoresist step and is therefore scalable. The gate region comprises two stack-gate transistors being formed in the side portions of the gate region having a select-gate transistor formed between two stack-gate transistors for the first embodiment of the present invention and having a planarized conductive island formed between a pair of sidewall dielectric spacers and over a common-drain diffusion region of a second conductivity type between two stack-gate transistors for the second embodiment of the present invention. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer being formed over a sidewall of a first-side/second-side region, an elongated control-gate layer being formed over an intergate dielectric layer, and an integrated floating-gate layer. The integrated floating-gate layer comprises a major floating-gate layer being formed over a thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of nearby raised field-oxide layers. The select-gate transistor comprises a planarized conductive island being formed over a gate-dielectric layer on a semiconductor surface and over two stack-gate transistors and an implanted region having a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop.
The first-side/second-side region comprises a pair of sidewall dielectric-spacer structures being formed over the sidewalls of nearby gate regions and comprises from top to bottom a planarized thick-oxide layer, a silicide layer, and a common-source conductive bus line formed over a flat bed, wherein the flat bed is formed by a common-source diffusion region and two etched raised field-
Elms Richard
Menz Doug
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