Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1995-11-06
1996-10-29
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523002, 36518402, G11C 800
Patent
active
055703208
ABSTRACT:
A memory circuit 300 is provided which includes first and second banks 201a and 201b of memory cells arranged in rows and columns. Row decoder circuitry 210 is provided for selecting a row in at least one of the banks in response to row address. Row address circuitry 208, 209 is included for providing a sequence of row addresses to the row decoder circuitry in response to a single row address received at an address port to memory circuitry 300. Column decoder circuitry 213 is provided for selecting columns in each of the banks 201 in response to a column address. Column address circuitry 211, 212 is provided for presenting a sequence of column addresses to the column decoder circuitry in response to a single column address received at the address port.
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Cirrus Logic Inc.
Nguyen Tan T.
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