Dual-bank memory module with stacked DRAM chips having a...

Details Dual-bank memory module with stacked DRAM chips having a... Dual-bank memory module with stacked DRAM chips having a...

2002-04-24

2003-04-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C257S777000, C438S109000, C361S729000, C361S735000

Reexamination Certificate

active

06542393

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to memory modules, and more particularly for stacking memory chips on memory modules.
Memory modules are extremely popularity today. Most personal computers (PC's) are shipped with sockets for memory modules so the PC user can later add additional modules, increasing the memory capacity of the PC. Other devices may also use memory modules designed for PC's. High-volume production and competition have driven module costs down dramatically, benefiting the buyer.
Memory modules are made in many different sizes and capacities, with the older 30-pin modules being replaced by 72-pin and 168-pin modules. The pins were originally pins extending from the module's edge, but now most modules are leadless, having metal contact pads or leads. The modules are small in size, some being about 5.25 inches long and 1.2 or 1.7-inch high.
The modules contain a small printed-circuit board substrate, typically a multi-layer board with alternating laminated layers of fiberglass insulation and foil or metal interconnect layers. Surface mounted components are soldered onto one or both surfaces of the substrate. Dynamic-RAM integrated circuits (IC's) or chips are commonly packaged in inexpensive surface-mount packages such as small-outline J-leaded (SOJ) packages, Plastic Leaded chip carriers (PLCC's), Thin Small-Outline Packages (TSOP) or small-outline (SO) packages.
The number of DRAM chips in a module depends on the capacity and data-width of the DRAM chips and the size of the memory module. For example, a memory module constructed from 64 Mega-bit×4-bit-output DRAM chips needs 16 of these 4-bit-wide DRAM chips to fill a 64-bit bus. The module has a capacity of 512 Megabytes (MB).
A memory module can have more than one bank. A two-bank memory module with a total capacity of 1024 MB can have two banks of 16 DRAM chips per bank, using 64M×4 chips.
FIG. 1
is a schematic of a memory module with two banks of DRAM chips. DRAM chips
12
-
16
form a first bank, while DRAM chips
22
-
26
from a second bank. A total of 16 DRAM chips
12
-
16
are in the first bank, while another 16 DRAM chips
22
-
26
form the second bank. When 64M×4 DRAM chips are used, each bank contains 512 MB.
Most signals are shared by all DRAM chips in both banks. For example, control signals such as RAS (row address strobe), CAS (column address strobe), write-enable, clocks, etc. and address lines are connected to all DRAM chips in both banks on the memory module. Data lines are each shared by one chip in each of the banks. Data lines D
0
-D
3
are shared by DRAM chip
12
in the first bank and DRAM chip
22
in the second bank. Likewise, data lines D
4
-D
7
are shared by DRAM chips
13
,
23
.
The banks are selected by chip-select signals. Only one chip select is activated at a time for the memory module. Chip select CS
1
activates DRAM chips
12
-
16
in the first bank, while chip select CS
0
selects DRAM chips
22
-
26
in the second bank. When the bank's chip select is not activated, the control signals are ignored by DRAM chips in the bank. The data lines are not driven by the non-selected bank of DRAM chips to prevent data conflicts.
FIG. 2
shows a prior-art double-bank memory module with stacked DRAM chips. While a 2-bank memory module can be constructed from non-stacked chips, twice as much surface area on the substrate would be needed. The memory module contains a substrate
10
, with surface-mounted DRAM chips
22
-
26
mounted directly to the front surface or side of substrate
10
, while more DRAM chips (not visible) are mounted to the back side or surface of substrate
10
. Eight stacks of DRAM chips can be mounted on the front surface of substrate
10
for bits
0
-
31
, while another eight stacks of chips can be mounted on the back side for bits
32
-
63
. Metal contact pads
20
are positioned along the connector edge of the module on both front and back surfaces. Metal contact pads
20
mate with pads on a module socket to electrically connect the module to a PC's motherboard. Holes and/or notches are sometimes used to ensure that the module is correctly positioned in the socket.
Often the number of DRAM chips desired on a memory module is larger than the available substrate surface area. One method to squeeze more DRAM chips to a module is to stack DRAM chips on top of one another. For example, DRAM chip
12
can be mounted directly on top of DRAM chip
22
. The leads or pins of upper DRAM chip
12
can be soldered to the leads or pins of lower DRAM chip
22
.
Usually DRAM chips from separate banks are stacked together. The DRAM chips stacked together share the same data lines as well as control signals. DRAM chips
12
-
16
of the first bank are stacked on top of DRAM chips
22
-
26
of the second bank. When chips are mounted to both surfaces of substrate
10
, two chips can be stacked together on the front surface and two chips can be stacked together on the back surface at each location of the substrate. Each surface can have mounting locations for 8 DRAM chips, for a total of 16 mounting locations (only 5 locations are shown in the FIG.). With stacking, a total of 32 DRAM chips can be mounted to substrate
10
.
FIG. 3
is an exploded view showing stacking of a pair of DRAM chips. Upper DRAM chip
12
of the first bank is mounted on the top of the stack, with lower DRAM chip
22
mounted below to the module substrate. One side of pins is shown, but pins are usually on two or even on all four of the four sides of a DRAM IC package.
Between upper DRAM chip
12
and lower DRAM chip
22
is thin printed-circuit board (PCB)
30
. Thin PCB
30
is a thin circuit board that can be made from fiberglass with printed metal layers on its two major surfaces. Thin PCB
30
has bonding pads
40
on its upper surface that are arranged for making contact with the pins S
1
-S
7
from upper DRAM chip
12
. The pins from upper DRAM chip
12
are soldered to these bonding pads
40
on the upper surface of thin PCB
30
during manufacturing.
The bottom surface of thin PCB
30
also has leads C
1
-C
7
that are arranged to make contact with the tops of the pins S
1
-S
7
of lower DRAM chip
22
. These leads C
1
-C
7
of thin PCB
30
are soldered to the pins S
1
-S
7
of lower DRAM chip
22
. Thus thin PCB
30
has bonding pads on the top surface that are soldered to pins of upper DRAM chip
12
, and has leads that are soldered to pins of lower DRAM chip
22
.
Each of the leads is connected to an upper bonding pad either directly above or through a drilled via or a metalized connection through the substrate of thin PCB
30
. Thus thin PCB
30
electrically connects pins from lower DRAM chip
22
to the pins of upper DRAM chip
12
that are directly above.
All of the address, data, RAS, CAS, clock, power, ground, and most other signals are shared among the two stacked DRAM chips
12
,
22
in this way by directly connecting corresponding pins S
1
-S
7
in upper and lower DRAM chips
12
,
22
. For example, pin
1
(S
1
) of upper DRAM chip
12
caries signal SI and connects through the first of bonding pads
40
on the top surface of thin PCB
30
to lead C
1
which is soldered to pin
1
(signal S
1
) of lower DRAM chip
22
.
While most pins of lower DRAM chip
22
are connected with the pins directly above of upper DRAM chip
12
, there are some exceptions. The chip-select pins are disconnected and re-routed by thin PCB
30
so that the stacked DRAM chips receive different chip-select signals. This allows one of the DRAM chips
12
,
22
to be selected and the other de-selected.
For example, chip select CS
0
connects to lower DRAM chip
22
through pin
3
. Chip select CS
0
controls the second DRAM bank that includes lower DRAM chip
22
. The connection from CS
0
to thin PCB
30
is broken by the removal of lead C
3
of thin PCB
30
. Without the C
3
lead, no connection is made between pin
3
of lower DRAM chip
22
and thin PCB
30
.
DRAM chips often include unused pins known as no-connect (NC) pins. These pins do not conn

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