Stock material or miscellaneous articles – Composite – Of addition polymer from unsaturated monomers
Reexamination Certificate
2000-06-20
2002-03-26
Elms, Richard (Department: 2824)
Stock material or miscellaneous articles
Composite
Of addition polymer from unsaturated monomers
C438S527000, C438S299000, C438S301000, C438S303000, C438S307000
Reexamination Certificate
active
06361874
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits with reduced gate over-melting during annealing.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
As MOSFET scaling continues (e.g., MOSFETs become smaller), ultra-shallow and highly-activated junctions are essential for optimum device performance. The lateral abruptness of source and drain extension is critical for controlling short-channel effects in sub-100 nanometer CMOS transistors. Yet, external resistances (S/D extension, contact resistance, etc.) play a significant role in device performance. Super doped extensions (SDE) rather than the conventional lightly doped drain (LDD) or highly doped drain (HDD) may be required to adequately reduce external resistances. Industry demands may require source and drain extensions shallower than 30 nm for sub-70 nanometer CMOS processes and active dopant concentrations over 1×10
21
dopants per centimeter cubed. Highly-activated junctions generally require large thermal budgets (high temperatures) while shallow junction formation requires low thermal budgets due to the adverse effects of thermal diffusion.
Recent advancements in low keV implantation of dopants has increased the challenge of providing sufficient dopant electrical activation. Current rapid thermal annealing processes (RTA) can cause undesired thermal diffusion and yet not provide sufficient electrical activation. The electrical activation can be limited by the solid solubility of the material that is doped. Accordingly, novel processes for activating dopants which do not affect the lateral abruptness of junction regions must be developed.
Thus, there is a need for a method of manufacturing ultra-shallow source and drain extensions with sufficient dopant activation. Further still, there is a need for transistors that have ultra-shallow junction source and drain extensions with aggressive scaling of lateral abruptness. Even further still, there is a need for an efficient method of manufacturing source and drain extensions that maximizes dopant activation ion implantation and minimizes short channel effects. Yet further, there is a need for a dual amorphization process that does not over-melt gate conductors.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes forming at least a portion of a gate structure on a top surface of a silicon substrate, providing a first pre-amorphization implant, doping the substrate for drain and source extensions, providing oxide spacers, providing a post-amorphization implant, doping the substrate to form deep source and drain regions, and thermally annealing the substrate. The gate structure includes a polysilicon gate conductor and is disposed on a top surface of a silicon substrate. The pre-amorphization implant creates a first amorphous region near the top surface of the substrate. The oxide spacers abut the gate conductor. The post amorphization implant creates a deep amorphous region in the substrate. Thermally annealing the substrate melts the first amorphous region, the second amorphous region and a portion of the gate conductor.
Another exemplary embodiment relates to a method of providing ultra-shallow drain/source extensions for field effect transistors associated with an ultra-large scale integrated circuit. The method includes forming gate structures on a top surface of a silicon substrate, providing a first amorphization implant, doping the substrate for the drain/source extensions, providing spacers, providing a second amorphization implant, doping the substrate to form source and drain regions, and thermally annealing the substrate. The gate structures include gate conductors. The first amorphization implant creates a first amorphous semiconductor region near the top surface of the substrate, and the second amorphization implant creates a deep amorphous semiconductor region in the substrate. The spacers abut the gate structures. The substrate is thermally annealed to form the ultra-shallow drain/source extensions. The thermally annealing step melts the first amorphous semiconductor region, the deep amorphous semiconductor region and a portion of the gate conductor.
Yet another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions. The method comprises steps of forming at least part of a gate structure including a gate conductor on a top surface of a semiconductor substrate, providing a shallow amorphization implant, doping the substrate, providing spacers, providing a deep amorphization implant, doping the substrate to form source and drain regions, and laser annealing the substrate. The gate structure includes a gate conducto
Advanced Micro Devices , Inc.
Elms Richard
Foley & Lardner
Owens Beth E.
LandOfFree
Dual amorphization process optimized to reduce gate line... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual amorphization process optimized to reduce gate line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual amorphization process optimized to reduce gate line... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867532