Dual addressing transistor active matrix display screen

Details Dual addressing transistor active matrix display screen Dual addressing transistor active matrix display screen

1986-06-16

1991-03-26

Brier, Jeffery A.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340718, 340784, G09G 336

Patent

active

050033026

DESCRIPTION:

BRIEF SUMMARY
The present invention concerns a dual addressing transistor active matrix display screen.
An active matrix display screen is a device formed by a mosaic of memory points distributed over all of the surface of a support. These memory points store the video signal throughout the time for which an image is displayed. An electronic transducer (for example a liquid crystal) is in contact with each memory point. This transducer is energised throughout the duration of an image whereas, in systems with no electronic memory, the transducer is activated only for the time the point is energised. The optical effect and the multiplexing rate are thus improved.
The thin-film transistor (abbreviation TFT) is well suited to the implementation of a device of this kind. Each memory point is then situated at the crossing of an addressing column and a line and consists of an addressing TFT and a capacitor. When the transducer is a liquid crystal the plates of the capacitors consist of the electrodes of the liquid crystal cell themselves. The memory point is thus reduced to a TFT and a capacitor of which one plate is formed by the electrode deposited on one wall of the cell containing the liquid crystal, the other plate consisting of the counter-electrode disposed on the other wall of the cell.
A structure like this is shown in FIG. 1. There is seen, on the one hand, a lower wall 10 carrying conductive columns 12 and conductive lines 14, a TFT 20 and a transparent electrode 22 and, on the other hand, an upper wall 24 covered by a counter-electrode 26 that is also transparent.
A device of this kind is addressed in the following manner. The lines are energised sequentially at a potential that corresponds to the grid voltage needed to turn on the TFT. For as long as this potential is applied to a line the video signals are applied successively to the various columns, the effect of which is to excite all the display points (or "pixels") in the line. Once energisation of one line has been completed that of the next is begun, and so on.
The image is thus displayed point by point, each point retaining a memory of the excitation received by virtue of the capacitor structure of each pixel. The only loss of charge results from the leakage current flowing through the addressing transistor when this is cut off. However, the equivalent resistance of this transistor is generally very high (10.sup.-- ohms) so that this effect is virtually of no consequence.
There are many known processes for fabricating active matrices using TFT and capacitors. FIG. 2 illustrates, by way of example, a technique described by A. J. Snell et al in an article entitled "Application of Amorphous Silicon Field Effect Transistors In Addressable Liquid Crystal Display Panels" published in "Applied Physics", 24, 357-362 (1981). The TFT is formed by a grid G of chromium deposited on an insulative substrate 30, a layer 34 of amorphous silicon (aSi), a drain D and an aluminium source S. The lower plate of the capacitor is formed by a layer 38 of tin and indium oxide. The connection between the TFT and the plate is made by the drain D extended by a tab 40 using a contact hole 42. The entire circuit is made up of a plurality of such structures laid out in matrix form. The grids G consist of connection lines 44 and the sources of columns 46.
In another known fabrication technique, differing from the previous one, the TFT has its source and drain contacts in the lower part and its grid in the upper part. This technique is described by N. Matsumura et al in an article entitled "Amorphous-Silicon Integrated Circuit" published in "Proceedings of the IEEE", vol. 68, No 10, Oct, 1980, pages 1349-1350.
Another known manufacturing process is more efficient than the previous two in the sense that it neccessitates only two levels of masking rather than five or six, as is the case in the two processes mentioned above. This technique is described in the published French patent No. FR-A-2533072 entitled "Procedede fabrication de circuits electroniques a base de transistors en couches mi

REFERENCES:
patent: 4112333 (1978-09-01), Asars et al.
patent: 4431217 (1984-02-01), Okubo
patent: 4641135 (1987-02-01), Hilbrink
Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid Crystal Display Panels, A. J. Snell, K. D. Mackenzie, W. E. Spcar, and P. G. LeComber, Applied Physics, 1981.
Proceedings of the IEEE, vol. 68, No. 10, Oct. 1980.

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