Dual adder burst control governor to signal when a data burst is

Details Dual adder burst control governor to signal when a data burst is Dual adder burst control governor to signal when a data burst is

1996-07-01

1998-11-03

Barry, Esq., Lance Leonard

Boots, shoes, and leggings

3642581, G06F 1200

Patent

active

058323023

ABSTRACT:
An improved apparatus and method for monitoring and controlling when a data phase in a burst transmission of data is about to end. The apparatus described interleaves dual adder circuits such that each dual adder circuit has more time to process incoming data. Distribution of the processing allows slower, lower cost components to be used in high speed applications. The described apparatus and method are particularly useful in peripheral component interconnect applications.

REFERENCES:
patent: 4759014 (1988-07-01), Decker et al.
patent: 5539891 (1996-07-01), Childers et al.
patent: 5619647 (1997-04-01), Jardine
patent: 5640518 (1997-06-01), Muhich et al.

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