DSP processor architecture with write datapath word...

Details DSP processor architecture with write datapath word... DSP processor architecture with write datapath word...

2005-12-20

2005-12-20

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06978287

ABSTRACT:
An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of common DSP functional blocks such as multiplier-accumulator (MAC) blocks may be improved. Delays may be further reduced by combining analysis operations with write or move operations.

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