DSP architecture for a FIR-type filter and method

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3647241, G06F 1710, G06F 1717

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057320047

ABSTRACT:
The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

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