DS3 - line interface linear array (lila)

Details DS3 - line interface linear array (lila) DS3 - line interface linear array (lila)

1988-11-02

1990-10-16

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

379394, H04B 300

Patent

active

049641166

ABSTRACT:
In a line interface circuit for binary data signals means are provided for compensating varying lengths of line in the receiving and/or transmission path. The output signal of a line equalizer controls a variable impedance circuit in such a way that attenuation of a line build out network is reduced if the output level of the line equalizer falls below a threshold. A transmit line build out network provides a frequency dependent attenuation of binary data by means of a control circuit, which supplies discrete attenuation values according to a logic word.

REFERENCES:
patent: 3568100 (1971-03-01), Torbos
patent: 3578914 (1971-05-01), Simond
patent: 3671886 (1972-06-01), Fudemoto et al.
patent: 4555788 (1985-11-01), Merril
patent: 4686686 (1987-08-01), Nakayama et al.
patent: 4785265 (1988-11-01), Molnar et al.
patent: 4827505 (1989-04-01), Takato et al.
EXAR Corporation Catalog, pp. 1-448; 1-449; 1-450; 1-451; 1-428; 1-429; 1-438; 1-439, Mar. 1985.

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