Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-02-28
2002-11-12
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S067000, C216S075000, C216S079000, C438S720000, C438S725000, C438S734000, C438S743000, C438S742000
Reexamination Certificate
active
06479396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to a dry method for removing polymer and oxide veils for vias disposed on a Tungsten layer resulting from etching and controlling or partially removing the tungsten base or interface layer to create an undercut of the via to provide better plug adhesion when the via is filled.
2. Description of the Prior Art
During the making of a semiconductor chip structure in which a tungsten layer is deposited on a substrate material, and in which an oxide is deposited on the tungsten layer as an interlevel dielectric (ILD), and on which a photoresist is subsequently placed on the interlevel dielectric, followed by etching and photolithographic resist removal, veils are created in the vias and on the tungsten layer. This is so because the vias are etched through insulators and the etch progress stops on the tungsten.
Unfortunately, the etch process causes organic-metal oxides, veils, and other materials to form on the tungsten as well as on the sidewalls of the vias. Additionally, there is a thin-oxide formed on the tungsten during etching and photolithographic resist removal that must be penetrated.
Removal of these veil materials has historically been accomplished using wet chemistries and therefore encumbered by the disadvantages associated with these wet chemistries.
FIG. 1
depicts a typical starting semiconductor structure wherein a substrate material
10
has a tungsten layer
11
deposited for subsequent patterning. An oxide layer as an interlevel dielectric (ILD)
12
is deposited on top of the tungsten layer, and a photoresist
13
is deposited on top of the ILD layer. In the process of forming this basic structure that is well known in the art, the oxide layer is patterned using photolithography and a typical photoresist, whereupon the oxide etch is performed using a plasma generated etching method employing various wet chemistries. However, during this etch, polymer veils
14
and oxide veils
15
are formed that are made up of metals, carbon, and oxide-based materials.
Nevertheless, when the resist is stripped using known plasma based or chemical based processes, these processes do not remove the veils formed during the etch. The problems encountered by virtue of these oxide and polymer veils are well known in the art.
Accordingly, there is a need in the art of stripping resist following etch of a semiconductor chip structure in which a tungsten layer is deposited on a substrate material, to be able to remove polymer and oxide veils from sidewalls of vias, to remove the thin oxide formed on the tungsten layer, and to control the tungsten interface and therefore high contact resistance after etch and photolithographic resist removal, by other than the wet chemistries now used.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a dry process for removal of polymer and oxide veils from sidewalls of vias and on the interface of a tungsten layer of a semiconductor following oxide etch of an interlevel dielectric.
Another object of the present invention is to provide a RIE (reactive ion etching) method for removal of polymer and oxide veil's from sidewalls of vias and on the interface of a tungsten layer of a semiconductor following oxide etch of an interlevel dielectric.
A further object of the present invention is to provide a dry process for removal of polymer and oxide veils from sidewalls of vias and on the interface of a tungsten layer of a semiconductor following oxide etch of an interlevel dielectric in a manner so as to avoid the high contact resistance when an insulator interface is not removed from the tungsten surface and to limit the attack on tungsten to avoid unacceptable tungsten loss.
A yet further object of the present invention is to provide improved C
1
contact adhesion after C
1
polymer removal to obtain a better surface for the tungsten contact to adhere to, as a result of the undercut of the C
1
via.
In general, the invention process is accomplished by:
depositing tungsten on a substrate material and patterning the tungsten;
depositing an interlevel dielectric of an oxide on the tungsten layer;
depositing a photoresist on the oxide layer and patterning the oxide layer using photolithography and photo resist;
performing an oxide etch using a plasma generated etching method, wherein oxide veils are formed of metals, and carbon and oxide based materials; and
removing the veil materials by RIE (reactive ion etching) to provide a dry polymer clean.
REFERENCES:
patent: 5853602 (1998-12-01), Shoji
patent: 5858878 (1999-01-01), Toda
patent: 6030901 (2000-02-01), Hopper et al.
patent: 6214744 (2001-04-01), Wada
patent: 6352938 (2002-03-01), Chen et al.
Clark, Jr. Phillip Gerard
Shen Amy Ying
Xu Han
Infineon Technologies Richmond LP
Powell William A.
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