Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2000-09-13
2003-04-29
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S952000, C438S585000
Reexamination Certificate
active
06555397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of removing anti-reflective coating films from circuit structures.
2. Description of the Related Art
Insulated gate field effect transistors (“IGFET”), such as metal oxide semiconductor MO field effect transistors (“MOSFET”), are some of the most commonly used electronic components in modem integrated circuits. Embedded controllers, microprocessors, analog-to-digital converters, and many other types of devices now routinely include millions of field effect transistors. The dramatic proliferation of field effect transistors in integrated circuit design can be traced to their high switching speeds, potentially low power dissipation, and is adaptability to semiconductor process scaling.
A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or doped polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. In some conventional processes, the first implant is performed self-aligned to the gate electrode to establish lightly doped drain (“LDD”) structures. In others, a pair of very thin dielectric sidewall spacers are formed adjacent to the gate electrode prior to the LDD implant to provide for a small lateral separation between the gate and the LDD structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode where no set of thin spacers preceded the LDD implant, or adjacent to the previously formed thin LDD spacers. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain to provide contact points for interconnection with later-applied global and/or local interconnect metallization.
The patterning of the polysilicon gate entails the formation of a photoresist mask on the deposited polysilicon film. A resist film is applied to the polysilicon layer and patterned into the desired shape for the poly gate/line. The resist patterning involves resist exposure followed by a solvent rinse. In the first step, the resist is exposed to light passed through a mask or reticle. The light changes the chemical properties of the resist, rendering the resist either soluble or insoluble in a solvent. The resist is then rinsed in the solvent to remove the soluble portions thereof. The exposure light is diffracted by passage through the reticle. As the diffracted light passes through the resist, some of the light rays are scattered while others strike underlying films and reflect upwards. The reflected light rays interfere with incoming rays and produce an interference pattern composed of a plurality of standing waves. The interference pattern can cause unwanted perturbations in the resist, such as stair-stepping and line width variations. The problem is more acute where the underlying film or films are highly reflective. Oxide and polysilicon represent two examples of such reflective films.
In order to reduce the deleterious effects of standing wave interference and light scattering produced by radiation reflected back from the substrate during photoresist exposure, an anti-reflective coating (“ARC”) is commonly formed on the polysilicon layer prior to the polysilicon gate etch. Following ARC deposition, photoresist is applied to the polysilicon layer and patterned, i.e. exposed and developed, to establish the desired pattern for the gate. The ARC and the polysilicon layer are then anisotropically etched to define the gate. The photoresist is stripped and the remaining portion of the ARC covering the gate is removed. If not removed, the ARC may interfere with subsequent silicidation or contact formation.
Silicon oxynitride and silicon nitride are two materials frequently used for ARC films. ARC film removal conventionally involves a two-step acid bath dip process. Initially, the ARC film is subjected to a hot bath of light concentration HF at about 65 to 85° C. Next, a dip in hot phosphoric acid is performed, again at about 65 to 85° C. If the composition of the ARC is not anticipated to include oxide, then the HF dip is sometimes skipped.
A number of disadvantages are associated with conventional ARC removal processing. To begin, the hot baths subject the substrate and the polysilicon lines to one or more thermal shocks. In sub-micron processing, such thermal shocks can lead to crystalline dislocations in the lattice structures of the substrate and the overlying polysilicon lines. Such crystalline defects may lead to line lift-off and device failure during subsequent processing steps. Another disadvantage is variations in the linewidth of the polysilicon lines. The hot acid baths will attack the sidewalls of the polysilicon gates or lines to some degree. If the amount of attack is known and repeatable, then the design rules may account for the loss. However, consistency in sidewall attack has proved difficult to attain. The difficulty stems from the fact that the acid solutions can be quickly depleted of reactants. Thus, successive lots of substrates may be subjected to acid baths with different compositions.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon structure are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching.
In accordance with another aspect of the present invention, a method of fabricating a conductor structure on a first workpiece is provided. A polysilicon film is formed on the first workpiece and an anti-reflective coating is formed on the polysilicon film. A mask is formed on a first portion of the anti-reflective coating while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the polysilicon film are etched. The mask and the anti-reflective coating are removed by isotropic plasma etching.
In accordance with another aspect of the present invention, a method of fabricating a conductor structure on a first workpiece is provided. A polysilicon film is formed on the first workpiece and a silicon oxynitride anti-reflective coating is formed on the polysilicon film. A photoresist mask is formed on a first portion of the silicon oxynitride anti-reflective coating while a second portion thereof is left unmasked. T
Bonser Douglas J.
Hussey, Jr. James H.
Purdy Matthew
Advanced Micro Devices , Inc.
Foong Suk-San
Fourson George
Honeycutt Timothy M.
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