Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-04-05
2004-07-13
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S716000
Reexamination Certificate
active
06762129
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a dry etching method for a material containing silicon, a method for fabricating a semiconductor device using the dry etching method, and a dry etching apparatus for implementing the dry etching method.
When dry etching is performed with respect to a material containing silicon (hereinafter referred to as the silicon-containing material) in the fabrication of a semiconductor device, a dry etching apparatus having a dual power source such as an inductively coupled plasma etching apparatus (ICP) has been used to miniaturize a semiconductor element and increase the precision thereof. The dry etching apparatus having the dual power source features separate and controlled application of first electric power (hereinafter referred to as source power) for generating a plasma of a process gas introduced into a chamber and adjusting the density of the plasma and second electric power (hereinafter referred to as bias power) for drawing ions (etching species) from the plasma into an object to be etched. The use of the dry etching apparatus having the dual power source provides high-accuracy processing properties. In a typical dry etching apparatus having a dual power source, the source power is applied to a coil or the like provided on an outer wall of the chamber and the bias power is applied to a sample stage provided in the chamber to carry the object to be etched.
The step of forming an isolation in a silicon substrate has conventionally used LOCOS (Local Oxidization of Silicon) for forming the isolation by locally oxidizing the silicon substrate masked with a nitride film. As feature sizes have been reduced increasingly, however, the problem has arisen that the isolation is larger than a desired size, which makes it difficult to provide an active region having a sufficient size. To solve the problem, STI (Shallow Trench Isolation) has been used as a replacement in which an isolation is formed by forming a trench in a silicon substrate, filling an oxide film in the trench, and then planarizing a surface of the silicon substrate including a surface of the oxide film by CMP (Chemical Mechanical Polishing). The foregoing dry etching apparatus having the dual power source is used to form the trench for isolation.
Herein below, a conventional method for fabricating a semiconductor device, specifically a method for forming a trench for isolation by etching a silicon substrate by using the dry etching apparatus having the dual power source will be described with reference to the drawings.
FIGS. 11A
to
11
D are cross-sectional views illustrating the individual process steps of the conventional method for fabricating a semiconductor device.
First, as shown in
FIG. 11A
, a first silicon oxide film
81
is formed on a silicon substrate
80
by thermal oxidation, followed by a silicon nitride film
82
formed on the first silicon oxide film
81
by using a film forming method such as CVD (chemical vapor deposition). Then, a resist pattern
83
having openings each corresponding to a region to be formed with an isolation is formed on the silicon nitride film
82
by photolithography.
Next, as shown in
FIG. 11B
, dry etching is performed with respect to the silicon nitride film
82
and to the first silicon oxide film
81
by using the resist pattern
83
as a mask, thereby patterning each of the silicon nitride film
82
and the first silicon oxide film
81
. Thereafter, the resist pattern
83
is removed by ashing and the silicon substrate
80
is cleaned.
Next, as shown in
FIG. 11C
, dry etching is performed with respect to the silicon substrate
80
by using the patterned silicon nitride film
82
as a mask, thereby forming trenches
84
for isolation in the silicon substrate
80
. A detailed description will be given to the dry etching step shown in FIG.
11
C. First, the silicon substrate
80
as an object to be etched is placed in the chamber (not shown) of the dry etching apparatus. Then, the chamber is evacuated till a specified degree of vacuum is reached and a gas required to etch the silicon substrate
80
(hereinafter referred to as a process gas), specifically a mixture of a halogen-containing gas such as Cl
2
or HBr and an oxygen gas is introduced into the chamber. Subsequently, a plasma of the process gas is generated by initiating the application of source gas and then ions in the plasma are drawn into the silicon substrate
80
by initiating the application of bias power. As a result, the ions in the plasma and an exposed portion of the silicon substrate
80
react with each other to form a volatile reaction product (such as a compound of silicon and chlorine). At this stage, dry etching is performed with respect to the silicon substrate
80
by evacuating the chamber and thereby exhausting the foregoing volatile reaction product from the chamber. Thereafter, the silicon substrate
80
is cleaned such that a deposit (such as a compound of the foregoing volatile reaction product and oxygen) formed on the silicon substrate
80
during dry etching is removed therefrom, whereby the trenches
84
are formed in the silicon substrate
80
.
Since the dry etching step shown in
FIG. 11C
requires processing accuracy as high as required by the processing of a gate electrode due to a reduced size of the isolation, a dry etching apparatus having a dual power source such as an inductively coupled plasma etching apparatus is used in the dry etching step.
Next, the portions of the silicon substrate
80
located adjacent the wall and bottom surfaces of the trench
84
are thermally oxidized by using an oxidation furnace in order to lower a surface state in the portions of the silicon substrate
80
. Then, a second silicon oxide film
85
is deposited on the silicon nitride film
82
by CVD to completely fill the trench
84
. Subsequently, a surface of the silicon nitride film
82
including a surface of the second silicon oxide film
85
is planarized by CMP such that the portions of the second silicon oxide film
85
located externally of the trenches
84
are removed. Thereafter, the silicon nitride film
82
is removed by wet etching and the first silicon oxide film
81
remaining on the surface of the silicon substrate
80
is removed by cleaning the silicon substrate
80
as shown in
FIG. 11D
, whereby isolations composed of the second silicon oxide film
85
filled in the trenches
84
are formed.
A description will be given herein below to a conventional method of applying the source power and the bias power in the dry etching step using the dry etching apparatus having the dual power source and shown in
FIG. 11C
(hereinafter referred to as the conventional dry etching method) and to the effect of the conventional dry etching method.
FIG. 12
shows an example of the respective time-varying effective values of the source power and the bias power in the conventional dry etching method. In
FIG. 12
, the time at which the application of the source power is initiated is used as the reference for power application time (0 second). In the present specification, the effective value of the bias power is the effective value of the bias power actually applied to the sample stage and the effective value of the source power is the effective value of the source power actually applied to the coil or the like. The effective value is defined herein as the value of an alternating power equal to the square root of the arithmetic mean of the squares of the instantaneous values taken throughout one complete cycle.
As shown in
FIG. 12
, the application of the bias power is initiated one second after the application of the source power is initiated. On the other hand, the effective value of the source power is set to 600 W, while the effective value of the bias power is set to 200 W.
FIGS. 13A
to
13
C are views showing the effect of the conventional dry etching method, specifically showing changes in the internal state of the chamber of the dry etching apparatus in the dry etching step shown in
FIG. 1C
, of which
FIG. 11A
shows the sta
Niko Hideo
Yamaguchi Takao
Yamashita Takeshi
Chen Kin-Chan
Nixon & Peabody LLP
Studebaker Donald R.
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