Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-12-20
2003-08-19
Hiteshaw, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S706000, C438S712000, C438S715000, C438S723000, C438S724000
Reexamination Certificate
active
06607986
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-372006, filed Dec. 28, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a dry etching method for eliminating a second insulating layer containing carbon atoms formed on a first insulating layer containing carbon atoms by use of activated reactive gas and a semiconductor device manufacturing method using the dry etching method.
A semiconductor device is required to have a more fine pattern with an increase in the integration density thereof. Further, an attempt is made to reduce an interconnection resistance and parasitic resistance in order to enhance the response speed.
In order to enhance the fine pattern technique of the semiconductor device, it is necessary to improve the resolution of a photoresist and it is effective to reduce the thickness of the photoresist in the development of the semiconductor device. Further, an antireflection layer is formed directly under a photoresist layer and the photoresist layer is patterned.
It is required to lower the interconnection parasitic capacitance in order to enhance the operation speed of the semiconductor device and a lowering in the dielectric constant (which is called Low-k layer) of an interlayer dielectric is studied. As the interlayer dielectric having a lowered dielectric constant, an organic based layer such as CF (fluorocarbon) based Teflon, a porous and relatively fragile inorganic layer such as an inorganic silicon oxide layer and an organic silicon oxide layer containing an organic component having carbon atoms in an inorganic layer can be given. The relative dielectric constant of the conventional oxide layer is approximately 4, but the relative dielectric constant of the above insulating layers is 3 or less. If an etching process is effected to form interconnection grooves and contact holes after a photoresist is patterned on the interlayer insulating layer, it is necessary to strip the photoresist in order to prepare for a case wherein an interconnection material or the like is filled in a later step.
In the conventional photoresist stripping method, a downflow ashing process for raising the wafer temperature to a high temperature of 200° C. or more and using process gas mainly containing oxygen gas is effected. In this method, the resist stripping process is realized by reacting carbon, oxygen, hydrogen atoms and the like in the photoresist with oxygen atoms in the active gas. It is considered that a reactive product obtained at this time contains CO
2
, CO, H
2
O and the like, but in order to attain a sufficiently high stripping rate, a method for raising the temperature of the semiconductor substrate to 200° C. or more to enhance the reactivity is normally used.
However, in the conventional photoresist stripping method, if a multi-layered layer having a layer containing carbon atoms is formed as an underlying layer, the carbon atoms of the underlying layer react with oxygen atoms in the active gas and are removed. Therefore, if the underlying layer of the photoresist layer is a Teflon based organic layer (Low-k layer) of CF series, the underlying layer is etched when the photoresist is stripped and there occurs a problem that a critical dimension bias (CD bias) occurs. Further, if the underlying layer is a layer (organic silicon oxide layer) formed of an inorganic layer containing carbon atoms, a carbon atom removed layer is formed on the surface of the underlying layer and a problem that the relative dielectric constant is changed occurs. At this time, since the underlying layer from which the carbon atoms have been removed is contracted, there occurs a problem that not only the CD bias is changed but also a stress is applied, thereby causing a crack.
Further, as a gas dielectric structure, a structure having a carbon layer buried in a porous insulating layer used as the underlying layer is known. The structure is formed by sequentially effecting processes for stripping the photoresist after interconnection grooves and contact holes are formed in the carbon layer, then filling barrier metal and interconnection material therein, and effecting a CMP (Chemical Mechanical Polishing) step. However, in the conventional method, there occurs a problem that carbon atoms buried in the underlying layer are ashed at the time of stripping the photoresist, the underlying layer is partly removed and, as a result, the CD bias occurs.
BRIEF SUMMARY OF THE INVENTION
This invention has been made in view of the above problems and an object of this invention is to provide a dry etching method and semiconductor device manufacturing method for preventing modification or deformation from occurring on the side surface of grooves when a second insulating layer is removed after the second insulating layer which is patterned and contains carbon is formed on a first insulating layer containing carbon and the grooves are formed in the first insulating layer with the second insulating layer used as a mask.
In order to attain the above object, a dry etching method of a first aspect of this invention comprises the steps of sequentially laminating a first insulating layer containing carbon and a second insulating layer containing carbon on a substrate; patterning the second insulating layer into a preset shape; forming grooves in the first insulating layer by etching the first insulating layer with the second insulating layer used as a mask; and removing the second insulating layer by use of a reactive gas containing carbon atoms and at least one of oxygen atoms, hydrogen atoms and nitrogen atoms without substantially modifying or deforming the side surface of the grooves formed in the first insulating layer.
It is preferable that the first insulating layer containing carbon atoms is one selected from a group consisting of a carbon layer, an organic silicon compound layer and an organic layer.
The second insulating layer containing carbon is a photoresist, for example.
A semiconductor device manufacturing method of a second aspect of this invention comprises the steps of sequentially laminating an insulating layer and photoresist each containing carbon on a semiconductor substrate; patterning the photoresist into a preset shape; forming at least one of contact holes and a interconnection grooves in the insulating layer by etching the insulating layer with the photoresist used as a mask; ashing and removing the photoresist by use of a gas containing carbon atoms and at least one of oxygen atoms, hydrogen atoms and nitrogen atoms; and depositing a metal interconnection layer in at least one of the contact holes and the interconnection grooves to form interconnections therein.
It is preferable that the insulating layer containing carbon is one of an organic silicon compound layer and an insulating layer of low dielectric constant containing carbon atoms.
A semiconductor device manufacturing method of a third aspect of this invention comprises the steps of sequentially laminating an insulating layer and a first photoresist on a semiconductor substrate; patterning the first photoresist into a preset shape; forming first interconnection grooves by etching the insulating layer with the first photoresist used as a mask; ashing and removing the first photoresist by use of a gas containing carbon atoms and at least one of oxygen atoms, hydrogen atoms and nitrogen atoms; burying a carbon layer in the first interconnection grooves; laminating a second photoresist on the insulating layer to cover the carbon layer; patterning the second photoresist into a preset shape; forming second interconnection grooves by etching the carbon layer with the second photoresist used as a mask; ashing and removing the second photoresist by use of a gas containing carbon atoms and at least one of oxygen atoms, hydrogen atoms and nitrogen atoms; depositing a metal interconnection layer in the second interconnection grooves to bury interconnections
Ichinose Hideo
Seta Shoji
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