Telecommunications – Radiotelephone system – Message storage or retrieval
Reexamination Certificate
2000-01-31
2003-09-23
Urban, Edward F. (Department: 2685)
Telecommunications
Radiotelephone system
Message storage or retrieval
C455S517000, C455S514000
Reexamination Certificate
active
06625440
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to communications systems and, more particularly, to an integrated avionics system with multiple data processing and radio functions sharing a common set of resources through asynchronous time tagged commands sorted in correct time order by a drum memory controller for efficient command execution at corresponding time-of-effectivity (TOE).
2. Related Art
In many communications systems such as modern integrated avionics systems, several signal processors, data processors and controllers are typically used to control a common set of resources such as radio frequency (RF) devices including receivers, transmitters, and antenna electronics and to perform multiple data processing and radio functions. These systems are deployed in a wide variety of avionics applications, including both ground and airborne environments for military and commercial users. Digitally controlled resources such as RF devices may also be used outside of avionics, such as in the telecommunications industry. For example, cellular telephone base stations often include RF devices controlled by digital hardware.
The task of coordinating shared resources (RF devices) in such communications systems is difficult. For example, many resources (RF devices) have no understanding of time, and are configured to-execute designated avionics functions immediately upon receipt of corresponding commands. Still different signal/data processors in such communications systems may need to setup different resources at various times prior to execution of those designated avionics functions, including, for example, communications, navigation and identification (CNI) purposes. As a result, communications data such as messages and/or commands may often be asynchronously generated from different signal/data processors at various times for execution. Yet there is no efficient way to coordinate and allocate such communications data in time order and to avoid message processing bottleneck between signal/data processors and shared resources.
One approach to coordinating shared resources is to use an intermediate processor to sort messages into a correct time order, and then store all the asynchronously received communications data from several signal/data processors in first-in, first-out (FIFO) queues. However, implementing storage and retrieval of such communications data under such an approach is both complicated and costly. Each FIFO queue must be loaded in time order and cannot be rearranged. Complex sorting software must be installed at the intermediate processor to sort all the asynchronously received commands in time order while often incurring message processing bottleneck. In addition, complex dedicated logic must be used to arbitrate retrieval of commands.
Therefore, it is desirable to provide a more efficient, yet simplified memory system and control mechanism for sorting all the asynchronously received command messages based on corresponding time tag (time stamp) into a correct time order in a seamless and straight forward manner.
SUMMARY OF THE INVENTION
Accordingly, various embodiments of the present invention are directed to a more efficient and yet simplified drum memory controller for use in a data communications system such as an integrated avionics system to sort command messages from different asynchronous processors into correct time order in a seamless and straight forward manner for timely execution of all command messages while avoiding the traditional software-based processor message sorting overhead and message processing bottleneck, and eliminating interactions between the asynchronous processes and boundary condition difficulties of zero or maximum time values storage.
In accordance with one aspect of the present invention, a drum memory controller is provided to receive data from asynchronous processors and control random access write and sequential read operations of a drum memory. The drum memory controller may comprise a drum memory having a predetermined number of rows and rings forming a plurality of memory locations arranged in a sequential time order; a random access write address generator which generates write addresses using a respective time tag, of incoming data for writing such data into memory locations of the drum memory in a random access time order; and a sequential reader which generates read addresses at a constant rate for reading out data stored in the memory locations of the drum memory across each row and then sequencing up in rows in a sequential time order.
Generally, the random access write address generator may correspond to a dedicated hardware logic implemented to determine the respective time tag of incoming data, and map such time tag into specific addressable memory locations of the drum memory. Similarly, the sequential reader may correspond to a dedicated hardware logic implemented to read through every memory location across a row of the drum memory in a sequential time order. The drum memory may be implemented by a single bank of random-access-memory (RAM) configured in rows and rings for storing all incoming data from different asynchronous processors using a common set of shared resources, for example, radio-frequency (RF) devices, including receivers, transmitters and antenna electronics. Each ring may be designated for different data communications function so as to preserve orthogonality between communications functions, and thereby eliminating contention and collision between the communications functions.
The sequential reader comprises a 13 &mgr;s counter which indicates when to begin reading from the start of each row of the drum memory in a sequential time order; an address generator which updates successive rows at every 13 &mgr;s tick from the counter; and a state machine which generates control signals to address physical memory locations of the drum memory for retrieving data from the drum memory.
In accordance with another aspect of the present invention, an overall data communications system is provided including such a drum memory controller control random access write and sequential read operations of data from different asynchronous processors. Such a data communications system may comprise a plurality of asynchronous processors configured to control radio-frequency (RF) devices, including, for example, receivers, transmitters, and antenna; a drum memory controller configured to receive data from the asynchronous processors and control random access write and sequential read operations of a drum memory via a random access write address generator and a sequential reader; and a RF bus controller configured to send data read from said drum memory to the RF devices for execution at respective time-of-effectivity (TOE).
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Mailleau Stephane
Shaler Barton G.
Antonelli Terry Stout & Kraus LLP
Bui, Esq. Hung H.
Chow C.
TRW Inc.
Urban Edward F.
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