Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2003-09-24
2004-12-21
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000, C315S169400
Reexamination Certificate
active
06833824
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving method for a plasma display panel to be used when potentials of panel electrodes are varied to predetermined potentials in periods of time other than a period of time when charge-collection is performed.
2. Description of the Related Art
Generally, a plasma display panel has various advantages. For example, the panel can be constructed to be thin, no flickering occurs in display, the display contrast ratio is high, large-screen display can be relatively easily performed, the response speed is high, and multicolor light emission is enabled by use of emissive type phosphors. Therefore, in recent years, plasma display panels are widely used in the fields of, for example, public-use wide-screen displays and color televisions.
FIG. 1
is a circuit diagram showing a configuration of a conventional plasma display panel. As shown in
FIG. 1
, the plasma display panel includes a panel
608
for performing display light emission, and driver circuits for controlling display contents and display luminance of the panel
608
.
A pair of primary electrodes is formed on the panel
608
. One of the primary electrodes is formed of a set of scan electrodes
606
-
1
to
606
-
n
, and the other one of the primary electrodes is formed of a set of sustain electrodes
605
-
1
to
605
-
n
. The primary electrodes are formed mutually parallel to the horizontal direction of the panel. Data electrodes
607
-
1
to
607
-N are formed perpendicular to (the vertical direction of) the primary electrodes. Pixels are to be formed at cross points of the primary electrodes and the data electrodes
607
-
1
to
607
-N. Thereby, the pixels are to be formed in a matrix on the panel
608
.
A scan driver circuit
602
is connected to the scan electrodes
606
-
1
to
606
-
n
to drive them. A sustain driver circuit
600
is connected to the scan driver circuit
602
. The sustain driver circuit
600
outputs sustain pulses that sustain light emission of the panel
608
. The scan driver circuit
602
and the sustain driver circuit
600
together form a scan-electrode driver circuit
612
.
The sustain electrodes
605
-
1
to
605
-
n
are incorporated into a common sustain electrode. A sustain-electrode driver circuit
601
is connected to the incorporated common sustain electrode as well as to the scan driver circuit
602
. The sustain driver circuit
601
outputs sustain pulses that sustain light emission of the panel
608
. The sustain-electrode driver circuit
601
contains a charge-collecting circuit not shown) and a sustain driver circuit (not shown) that are series-connected to each other therein. One end of the charge-collecting circuit is connected to the scan driver circuit
602
, and one end of the sustain driver circuit is connected to the common sustain electrode. Thereby, the charge-collecting circuit is parallel-connected to the panel
608
, and the charge-collecting circuit and the capacitance between the set of the scan electrodes and the set of the sustain electrodes form a resonant circuit. Data-driver circuits
604
a
and
604
b
each drive N/2 of the data electrodes
607
-
1
to
607
-N; and they are disposed at two end portions of the panel
608
that oppose each other on the same plane. The data driver circuits
604
a
and
604
b
are connected to the data electrodes
607
-
1
to
607
-N.
A scan-driver controller
609
a
is connected so to the scan driver circuit
602
, a data-driver controller
610
a
is connected to the data-driver circuit
604
a
, and a sustain-driver controller
611
a
is connected to the sustain driver circuit
600
. A controller circuit
603
a
is configured to include the scan-driver controller
609
a
, the data-driver controller
610
a
, and the sustain-driver controller
611
a
. Similarly, a scan-driver controller
609
b
is connected to the scan driver circuit
602
, a data-driver controller
610
b
is connected to a data-driver circuit
604
b
, and a sustain-driver controller
611
b
is connected to the sustain-electrode driver circuit
601
. A controller circuit
603
b
is configured to include the scan-driver controller
609
b
, the data-driver controller
610
b
, and the sustain-driver controller
611
b
. Scan-driver circuits
609
a
and
609
b
each control n/2 of outputs from the scan driver circuit
602
to the scan electrodes
601
-
1
to
601
-
n.
Hereinafter, a driving method for the conventional plasma display panel configured as described above will be described.
FIG. 2
is a timing chart regarding the scan electrodes
606
-
1
to
606
-
n
and the sustain electrodes
605
-
1
to
605
-
n
of the conventional plasma display panel shown in FIG.
1
.
First, an erase pulse is applied to the set of the scan electrodes
606
-
1
to
606
-
n
to slowly reduce its potential and to generate erase discharges. Thereby, wall charges accumulated in the scan electrodes
606
-
1
to
606
-
n
are erased (a sustain erase period).
Subsequently, to obtain stabilized write-discharge characteristics in a scan period for selecting display pixels, active particles and wall charges are generated in a discharge gas space, First, a priming discharge pulse is applied to the scan electrodes
606
-
1
to
606
-
n
to generate discharges at all the pixel on the panel
608
(a priming period). Subsequently, a priming discharge-erasing pulse is applied to the scan electrodes
606
-
1
to
606
-
n
for eliminating charges which impede write discharge and sustain discharge, among the wall charges generated through the aforementioned priming discharge (a priming erase period).
Specifically, first, in the priming period, the priming discharge pulse is applied to the scan electrodes
606
-
1
to
606
-
n
to generate discharges at all the pixels. Subsequently, in the priming erase period, the sustain-electrode
605
-
1
to
605
-
n
-side potential is increased to a sustain voltage level Vs. Concurrently, the priming discharge-erasing pulse for slowly reducing the potential caused by the priming discharge pulse is applied to the scan electrodes
606
-
1
to
606
-
n
to cause them to generate erase discharges. Thereby, stored wall charges caused by the priming discharge pulse are erased.
Subsequently, sequential scanning pulses are applied to the scan electrodes
606
-
1
to
606
-
n
. In synchronization with the scanning pulses, data pulses are selectively applied to the data electrodes
607
-
1
to
607
-N of pixel to be displayed. In this manner, write discharges are generated at portions of pixel to be displayed to thereby create wall charges (a scan period).
Subsequently, voltages are alternately applied between the scan electrodes
606
-
1
to
606
-
n
and the sustain electrodes
605
-
1
to
605
-
n
; and discharges generated thereby are used to perform display operation (a sustain period). The luminance of the display is determined according to the number of repetitions of the alternate voltage application performed between the scan electrodes
606
-
1
to
606
-
n
and the sustain electrodes
605
-
1
to
605
-
n.
Hereinafter, a description will be made regarding a control method for potentials of the scan electrodes and the sustain electrodes of the above-described plasma display panel.
FIG. 3
is a circuit diagram showing a conventional sustain driver circuit in the plasma display panel. As shown in
FIG. 3
, a switch S
1
for clamping a sustain-electrode
605
-
1
to
605
-
n
-side potential to a power voltage is series-connected to a switch S
2
provided for clamping the sustain-electrode
605
-
1
to
605
-
n
-side potential to a ground potential. A clamping circuit on the sustain-electrode side is formed of the switches S
1
and S
2
. A circuit line including a switch S
7
and a resistor R
1
for slowly increasing the sustain-electrode
605
-
1
to
605
-
n
-side potential is series-connected to a circuit line including a switch S
8
and a resistor R
2
for slowly reducing the sustain-electrode
605
-
1
to
605
-
n
-side potential. A slope circuit on the sustain-electrode side
Ide Kazuyoshi
Shirasawa Hiroshi
Hayes & Soloway P.C.
Mengistu Amare
Pioneer Corporation
Sheng Tom
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