Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2003-06-24
2008-03-11
Shankar, Vijay (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S095000, C345S204000, C345S210000, C345S213000
Reexamination Certificate
active
07342561
ABSTRACT:
A drive control circuit supplies a gate voltage so that display quality is not degraded even in a case where a vertical scanning frequency or a horizontal scanning frequency is changed. The circuit includes a timing controller for detecting a change of a horizontal scanning frequency, a gate voltage generating circuit for generating two kinds of gate-on voltages Va and Vb (Va<Vb), and a switch for outputting one of the gate-on voltages Va and Vb from the gate voltage generating circuit in accordance with an output of the timing controller. The timing controller includes a counter for counting the number of clocks for one horizontal period, and a comparator for comparing a count result with a threshold value. When the horizontal scanning frequency is in a normal state, the low gate-on voltage Va is outputted, and when the horizontal scanning frequency exceeds a predetermined threshold value, that is, the count value falls below a threshold value, the high gate-on voltage Vb is outputted.
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Furukoshi Yasutake
Hiraki Katsuyoshi
Katagawa Koichi
Kobayashi Tetsuya
Nishido Masanori
Greer Burns & Crain Ltd.
Shankar Vijay
Sharp Kabushiki Kaisha
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