Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Patent
1995-01-05
2000-07-18
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
257240, 257241, 257225, 257249, H01L 27148, H01L 29768
Patent
active
060910925
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a charge-coupled device.
The invention will be more particularly described for the production of large-sized photodiodes coupled to charge-reading registers, but it also relates more generally to any type of charge-coupled device.
BACKGROUND OF THE INVENTION
Large-sized photodiodes are intended to provide low-illumination signals.
According to the prior art, the charges created in large-sized photodiodes can be completely driven to the read register only if a charge background, called the driving charge, in injected into the diode.
This driving charge is then transferred and read at the same time as the useful signal created by the photodiode. Such a system has many drawbacks. Over and above the fact that it requires a charge injection device, it decreases the output dynamics by increasing the noise level.
The invention does not have these drawbacks.
SUMMARY OF THE INVENTION
The subject of the present invention is a photodiode comprising a photosensitive zone enabling charges to be generated under the effect of light and of a storage gate intended to store the charges thus generated, characterized in that it comprises means for draining away the charges to the storage gate. These means are mainly produced by narrow gates of varying width and electrically connected to the storage gate, the widening of which is progressive on moving closer to the storage gate. Under the effect of a DC voltage applied to the gates, a potential well of increasing depth appears beneath each gate, enabling the electrons created in the photosensitive zone to be collected and drained away to the storage gate.
An advantage of the invention consists therefore in improving the electrical performance of large-sized photoelectric diodes.
More generally, the invention also relates to a charge-coupled device comprising a semiconductor substrate and means for draining away charges from a first semiconductor zone to a second semiconductor zone on the substrate, these means including at least one insulated conducting gate connecting the two semiconductor areas and raised to a potential sufficient to create a potential well in the semiconductor substrate, characterized in that the insulated gate has a width progressively increasing from the first zone to the second zone, this width being sufficiently narrow for the potential well to have a depth progressively increasing from the first area to the second area.
BRIEF DESCRIPTION OF THE DRAWING
Other characteristics and advantages of the invention will appear on reading about the embodiments made with reference to the herein appended figures in which:
FIG. 1 represents the potential well existing beneath an insulated gate for two different values of the voltage applied to the gate;
FIG. 2 represents the potential wells existing beneath three narrow insulated gates of different widths, for the same value of the voltage applied to the gate;
FIG. 3 represents a photodiode according to a first embodiment of the invention;
FIG. 4 represents a detailed sectional view of FIG. 3;
FIG. 5 represents a photodiode according to the preferred embodiment of the invention;
FIG. 6 represents a detailed sectional view of FIG. 5.
In all the figures, the same references designate the same elements.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 represents the potential well existing beneath an insulated gate of width L1, for two different values (V1, V2) of the voltage applied to the gate.
A first curve C1 corresponds to a voltage V1 and a second curve C2 corresponds to a voltage V2 greater than V1. As is known to the person skilled in the art, the potential well P deepens as the applied voltage is increased.
These potential wells are uniform over the entire width of the gate except in the transition zones Z1, Z2 located on the edges of the gate, since the potential well does not reach its value immediately.
FIG. 2 represents the potential wells existing beneath three narrow gates of different widths (L2, L3, L4), for a first value (V) of the volta
REFERENCES:
patent: 3995302 (1976-11-01), Amelio
patent: 4839911 (1989-06-01), Boucharlat
patent: 5182622 (1993-01-01), Iizuka et al.
patent: 5239192 (1993-08-01), Hirota
patent: 5286989 (1994-02-01), Yonemoto
patent: 5365093 (1994-11-01), Kund
Caranhac Sophie
Thenoz Yves
Fenty Jesse A.
Saadat Mahshid
Thomson-CSF Semiconducteurs Specifiques
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