Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-09-30
2002-01-22
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06340964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
The present invention relates to a driving device and a liquid crystal display device which are suited for a simple matrix type liquid crystal display element to be driven by a driving method in which a plurality of lines are simultaneously selected.
2. DISCUSSION OF BACKGROUND
Conventionally, as driving methods for a simple matrix liquid crystal display device, there are a driving method based mainly on a so-called line successive driving system (a conventional Example 1) and a multiple line simultaneously selecting/driving method in which row electrodes are simultaneously selected or a multiple line addressing method (hereinbelow, referring to as a MLA driving method) (a conventional Example 2).
The conventional Example 1 is a driving method in which scanning voltages are successively applied to each row electrode, and at the same time, column voltages are applied to a plurality of column electrodes whereby brightness controlling voltages are applied to each of the row electrodes. Further, display dots are controlled to have transmittances in response to average effective voltages applied during a time in which the voltages are once applied to all the row electrodes (hereinbelow, referred to as a frame period). A predetermined picture image is displayed for each frame period.
The conventional Example 2 is a driving method as follows. All the row electrodes constituting a display surface area are divided into simultaneously selected groups each comprising a plurality of row electrodes, and scanning voltages are simultaneously applied to each of the row electrodes of the simultaneously selected groups. Further, column voltages are applied to a plurality of column electrodes at the same time of the application of the scanning voltages so that selection voltages are applied to a plurality of liquid crystal pixels to which the column voltages are simultaneously applied. The above-mentioned operation is repeated at least the same number of times as the simultaneously selected number of row electrodes.
As a result, the display dots are controlled to have transmittances in response to average effective voltages applied during a time in which the above-mentioned repeated operations complete (1 frame period), and a picture image is formed for each frame period.
In this conventional Example 2, the column voltages applied to column electrodes are voltages obtained by multiplying “a unit column voltage” with values determined by performing matrix operations of display data corresponding to a plurality of simultaneously selected row electrodes and a scanning voltage applied to the simultaneously selected row electrodes.
The maximum value of magnifying power obtained by the matrix operations suffers restriction by an orthogonal matrix for the scanning voltage used for the matrix operations. It takes at most a larger value between the number of rows or the number of columns in the matrix. As examples of the conventional Example 2, there are JP-A-6-27907, U.S. Pat. No. 5,262,881, JP-A-8-234164 and so on.
The above-mentioned liquid crystal display device has been used as a display device for a man-machine interface with the progress of highly intelligent society. In recent years, it is widely used not only for a desktop type personal computer but also for a notebook type personal computer, PDA (a portable information terminal) or a portable telephone, which is suitable for carrying, taking an advantage of thin and light in weight. As a result, in the development of the liquid crystal display device, improvement has been made to provide a large surface area, and on the other hand, improvements of reducing the weight and power consumption rate have been made.
In such liquid crystal display device, various measures have been taken to lower the power consumption rate. In more detail, there are measures to form a liquid crystal display element capable of responding to a low effective voltage, or to use a reflective type liquid crystal display element without requiring a backlight.
Further, as a conventional Example 3, there is a publication “general-purpose addressing technology for an effective value response type liquid crystal display device (a report of SID meeting 1988, p. 80-p.85)” which reports the relation between the MLA driving method and consumption power. The conditions indicated by the conventional Example 3 are “L={square root over (M)} (provided M represents the total number of row electrodes for a display picture surface and L represents a number of simultaneously selected rows)”, and the optimum bias ratio at which a ratio of an effective voltage at an ON display time to an effective voltage at an OFF display time becomes the maximum (B
best
=maximum column voltage/scanning voltage=VC/VR). The publication reports that when the MLA driving was conducted under the above-mentioned conditions, a driving voltage for the liquid crystal display device can be reduced in comparison with that by a line successive driving method.
In JP-A-9-277650, when L≠{square root over (M)} and the MLA driving is conducted under a condition other than using the optimum bias ratio, the ratio of an effective voltage at an ON display time to an effective voltage at an OFF display time does not show the maximum value. However, it is possible to set a supplied voltage to be lower. Further, in a case of producing a one-chip LSI capable of carrying out multiplex driving at a duty ratio of about {fraction (1/80)}, it was possible to integrate a driving circuit by a semiconductor manufacturing process for a 5-V standard logic IC. Further, capability of not only low consumption power but also reduction of manufacturing cost was shown (a conventional Example 4). On the other hand, for reducing power consumption rate by contriving a circuit structure, there is a method of lowering a clock frequency and conducting a parallel treatment.
Operations of the conventional Example 1 will be described with reference to
FIGS. 7 and 11
.
FIG. 7
is a block diagram showing a controller-attached driving device
201
for driving a “64 row×132 column”-dot matrix type liquid crystal display element.
Interface signals I/F are inputted from an outer source to a controller 1. Row address signals ADRS and a read/write signal R/W are supplied from the controller
1
to a memory
2
. Data DATA are supplied from an outer source to the memory
2
.
RAMs for display data are built in the memory
2
, and 1 dot in the built-in RAM corresponds to 1 dot in the liquid crystal panel in a one-to-one relation. The memory
2
decodes the row address signals ADRS from the controller
1
to output in parallel data (1 bit*132) for 1 row corresponding to the address signals, the outputted data being latched in line buffers
3
in synchronism with a clock.
A column voltage generating circuit
11
decodes display data (1 bit*132) from the line buffers
3
and a signal, for providing an alternate current to liquid crystal, i.e., a polarity inversion signal POL-CHG, supplied from the controller
1
, and the decoded signals are supplied to a level shifter in which column voltages are suitably selected among levels of “V0, V2, V3, V5”. The selected column voltages are outputted to the liquid crystal panel
10
in synchronism with a clock CLK.
When rows are sequentially selected in a form of shift register in synchronism with the clock CLK, a row voltage generating circuit
9
decodes the polarity inversion signals POL-CHG and a value of register indicating selection or non-selection, and the decoded signals are supplied to a level shifter in which row voltages are formed suitably among “V0, V1, V4, V5”, the formed row voltages being outputted to the liquid crystal panel
10
. In this case, when the row voltage generating circuit
9
selects then throw, synchronization is taken so that the column voltage generating circuit
11
outputs column voltages as data corresponding to the n th row in RAM.
Driving waveforms in a driving state are shown in FIG.
11
. After a change of th
Kitamura Masakazu
Nagai Makoto
Nakazawa Akira
Tamai Kiyoshi
Mengistu Amare
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Optrex Corporation
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