Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-06-28
2011-10-04
Lefkowitz, Sumati (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C377S064000, C377S074000
Reexamination Certificate
active
08031158
ABSTRACT:
A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.
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Cho Nam-Wook
Jang Yong-Ho
Yoon Soo-Young
Carter III Robert E
Lefkowitz Sumati
LG Display Co. Ltd.
McKenna Long & Aldridge LLP
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