Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-02-18
2002-12-24
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C341S144000, C341S150000
Reexamination Certificate
active
06498596
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a driving circuit of a display device and a liquid crystal display device. More particularly, the invention relates to those having a simple structure, ensuring representation of good-quality images, and very easy to change the gradation of display.
As one type of flat displays used in personal computers, thin-type television receivers, etc., there is a display using a plurality of pixels having a capacitive load. An example thereof is liquid crystal displays.
So-called “active matrix type liquid crystal displays” using a pixel switching element like thin-film transistor (TFT) or thin film diode (TFD) for each pixel provide clear images, and have a high-density display ability equivalent to or higher than that of CRT. In particular, TFT liquid crystal displays (TFT-LCD) using thin film transistors as pixel switching elements are under active developments toward their practical use.
TFT typically uses amorphous silicon or polycrystalline silicon as its semiconductor active layer (channel, source and drain regions). For years, vigorous energy is being paid toward development of TFT-LCD of a driving circuit built-in type, in which scanning line driving circuits and video signal line driving circuits are formed together with pixel TFT on a transparent insulating substrate. This structure enables extending the effective display area of the transparent insulating substrate of a liquid crystal display and reducing the manufacturing cost.
TFT-LCD of this driving circuit built-in type includes on its pixel substrate a digital-analog converter circuit (hereinafter abbreviated DAC) for converting digital signals input as video signals from outside into analog signals.
However, conventional driving circuit built-in TFT-LCDs involved the problem that when the bit number of digital input signals was increased for the purpose of attaining higher definition of display images, DAC was enlarged in size and hence narrowed the effective display area of the screen. This problem is discussed below with reference to the drawings.
FIG. 56
is a conceptional diagram showing the structure of a capacitor-arrayed DAC used in conventional liquid displays. DAC shown here is of a parallel input type and includes a switch control circuit
41
, reference voltage source
42
, switch array
43
, capacitor array
44
, reset switch
45
and buffer amplifier
46
.
In the example shown here, digital data of
6
bits such as (B
6
, B
5
, . . . B
1
) are input in parallel as video signals.
The capacitor array
44
includes capacitors more by one than the number of bits of the digital data. Capacitance values of these capacitors are weighted in six different values from C through C/32 depending upon the binary coding. These capacitors are commonly connected at one end of each thereof, and connected to a vides signal line via the amplifier
46
. The capacitors are connected at the other end of each thereof selectively to a reference voltage Vs or the ground potential by MOS switches of the switch array
43
.
Each switch of the switch array
43
is directly controlled by binary data of an input which coincides with the capacitance weighting order of the capacitors.
In the example shown in
FIG. 56
, 6-bit conversion is possible. That is, when the parallel data (B
6
, B
5
, . . . B
1
) are input, the output voltage Vout is expressed by the following equation.
V
out
=
∑
i
=
1
6
B
i
·
2
(
i
-
7
)
·
Vs
(
1
)
This DAC, however, needs (n+1) capacitors for converting digital data of n bits. Therefore, in order to ensure high definition image display with a high display gradation by increasing the number of bits, the problem of a dimensional increase of the circuit inevitably occurs. In case of liquid crystal displays having a built-in driving circuit, dimensional increase of the DAC circuit makes it difficult to keep a sufficient effective pixel area, and causes the problem that the size of the display need be increased, and the weight becomes heavy.
On the other hand, in DAC of
FIG. 56
, since the capacitors in the capacitor array
44
must be weighted in capacitance so as to correspond to the binary coding, more and more accurate control of their capacitance values must be guaranteed as the number of bits increases. Therefore, the design and manufacturing margins are strict, and the production yield is liable to decrease.
Another problem with conventional DAC as shown in
FIG. 56
lies in that digital data it can convert is fixed in number of bit. That is, the gradation of video signals it can handle is fixed to a predetermined value according to the circuit arrangement of DAC, and it cannot be changed later. This means, in a personal computer, for example, that users cannot readily change the display mode depending on the content to be displayed.
Under the circumstances, Japanese Patent Laid-Open Publication No. H7-72822 includes description about the use of serial DAC made up of two capacitor elements. This structure, however, was limited in increasing the data processing speed because it required different periods for digital-analog conversion and input of analog signals into capacitor elements or output of digital signal from the capacitor elements.
SUMMARY OF THE INVENTION
The invention has been made starting with the recognition of the above-explained problems. It is therefore an object of the invention to provide a display device driving circuit and a liquid crystal display device enabling the use of a small-scaled circuit, ensuring good-quality images and enabling free changes of the display gradations.
To attain the object, the basic structure of the invention is made up of a reference voltage selecting circuit for exclusively selecting and outputting one of a plurality of reference voltages in response to individual bit signals of serial data of a plurality of bits which are time-serially input, a first capacitor element connected to the reference voltage selecting circuit to hold a reference voltage output from the reference voltage selecting circuit, a second capacitor element connected to the first capacitor element through a connection circuit to hold an electric charged distributed from the first capacitor element due to a short-circuit of the connection circuit at a timing prior to the input of individual signals into the reference voltage selecting circuit, and an output line which outputs the voltage held in the second capacitor element as a display signal.
That is, the display device driving circuit according to the invention is one configured to input digital data and output it after convert it into an analog video signal, which comprises a first capacitor, a selecting circuit introducing one of bits of the digital data to determine the charge voltage of the first capacitor as a first voltage when the value of the bit is “1” but determine the charge voltage of the first capacitor as a second voltage different from the first voltage when the value of the bit is “0”, a second capacitor, and a connection circuit which connects the first capacitor and the second capacitor to reallocate their charging electric charges so as to equalize their charging voltage, such that the charging voltage of the first capacitor or the second capacitor obtained by activating the selecting circuit and the connection circuit in this sequence for each of the bits of the digital data from its most significant bit to the least significant bit be output as the analog video signal.
Based on the basic structure shown above, the first display device driving circuit according to the invention is a driving circuit of a display device including a digital-analog converter circuit which introduces a digital data and outputs an analog video signal, in which the digital-analog converter circuit has an input capacitor parallel type structure including: a reference voltage selecting circuit which is responsive to each of bit signals of time-serially input data of a plurality of bits to exclusively select and output one of a plurality of refere
Hayashi Hirotaka
Karube Masao
Motai Tomonobu
Nakamura Kazuo
Nakamura Takashi
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