Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1997-06-11
2001-10-02
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S089000
Reexamination Certificate
active
06297813
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving circuit for an active matrix type flat display device. More particularly, the present invention relates to a driving circuit for a liquid crystal display device which realizes gray-level display with 256 or more gray levels.
2. Description of the Related Art
FIG. 17
shows a configuration of a conventional driving circuit corresponding to one output of a 3-bit digital driver.
The driving circuit of
FIG. 17
includes a sampling memory
131
, a hold memory
132
, and an output circuit
133
. In response to a rising edge of a sampling pulse T
smp
, 3-bit digital data D
0
to D
2
are stored in the sampling memory
131
. The digital data stored in the sampling memory
131
are then transferred in response to a rising edge of an output pulse OP to the hold memory
132
to be held therein. The output circuit
133
outputs one of gray level voltages V
0
to V
7
supplied externally in accordance with the values of the digital data held in the hold memory
132
as an output voltage Out.
FIG. 18
shows a configuration of the output circuit
133
which includes a 3-to-8 decoder
141
and eight analog switches ASW
0
to ASW
7
. The decoder
141
turns on one of the analog switches ASW
0
to ASW
7
in accordance with the values of the digital data. A gray level voltage supplied to the turned-on analog switch is output as the output voltage Out.
A digital driver having the configuration shown in
FIGS. 17 and 18
has advantages of simple structure and small power consumption and thus has been widely used. Such a digital driver is described, for example, in H. Okada et al., “Development of a low voltage source driver for large TFT-LCD system for computer applications”, 1991, International Display Research Conference, pp. 111-114.
The conventional digital driver having the above configuration requires the same number of gray level sources as the number of gray levels to be displayed. This causes no problem for a 3-bit digital driver, but may cause a problem when a digital driver is driven with more than 3 bits because the number of required gray level sources becomes too large. Specifically, it is practically impossible to realize a 6 or more bit digital driver with the above configuration to provide a display with a large number of gray levels.
To overcome the above problem, various techniques have been proposed for realizing a display with a large number of gray levels by generating interpolation voltages between gray level voltages supplied externally.
One example of such techniques is disclosed in Japanese Laid-Open Patent Publication No. 5-273520, which describes a circuit for generating interpolation voltages between adjacent gray level voltages by dividing the gray level voltages by use of resistances in a driver. Hereinbelow, this technique of generating interpolation voltages by use of resistance is referred to as a “resistance division technique”.
FIG. 19
shows a driving circuit
151
and a voltage dividing circuit
152
described in Japanese Laid-Open Patent Publication No. 5-273520 mentioned above. The driving circuit
151
corresponds to one output of a 4-bit digital driver.
The voltage dividing circuit
152
divides five external gray level voltages V
0
, V
4
, V
8
, V
12
, and V
15
by use of resistances to generate one or more interpolation voltages between every two adjacent gray level voltages. As a result, total 16 voltages V
0
to V
15
composed of the five gray level voltages and
11
interpolation voltages are supplied to the driving circuit
151
.
The driving circuit
151
selects one of the 16 voltages V
0
to V
15
supplied from the voltage dividing circuit
152
, and outputs the selected voltage via a buffer amplifier
157
.
Referring to
FIGS. 20A
,
20
B,
21
, and
22
, an application of the technique disclosed in Japanese Laid-Open Patent Publication No. 5-273520 mentioned above to a 6-bit digital driver will be described.
FIG. 20A
shows a configuration of a voltage dividing circuit
162
, which divides nine external gray level voltages V
0
, V
8
, V
16
, V
24
, V
32
, V
40
, V
48
, V
56
, and V
64
by use of resistances to generate seven interpolation voltages between every adjacent gray level voltages. As a result, 64 total voltages V
0
to V
63
composed of eight gray level voltages and
56
interpolation voltages are supplied to a driving circuit
161
.
FIG. 20B
shows an array of eight resistances connected in series between the gray level voltages V
0
and V
8
shown in FIG.
20
A. Such an array of eight resistances is also provided between any of the other adjacent gray level voltages.
FIG. 21
shows a configuration of the driving circuit
161
which corresponds to one output of the 6-bit digital driver.
FIG. 22
shows a configuration of an output circuit
173
of the driving circuit
161
of FIG.
21
. The output circuit
173
includes a 6-to-64 decoder
181
and
64
analog switches ASW
0
to ASW
63
. The 64 voltages V
0
to V
63
output from the voltage dividing circuit
162
are supplied to the analog switches ASW
0
to ASW
63
, respectively. The decoder
181
turns on one of the analog switches ASW
0
to ASW
63
in accordance with the value of digital data. A voltage supplied to the turned-on analog switch is output via a buffer amplifier
183
as an output voltage Out.
An “oscillating voltage technique” is also known as a technique for realizing a display with a large number of gray levels by generating interpolation voltages between gray level voltages supplied externally. The oscillating voltage technique is based on a principle completely different from that of the resistance division technique described above. The principle of the oscillating voltage technique will be described.
It is generally known that a periodic function can be expanded to a Fourier series as long as it can be integrated. Therefore, a voltage which oscillates between a voltage v
i
and a voltage v
j
at a duty ratio of m:n as shown in
FIG. 23
is represented by Expression (1) below as a function f(t).
f
(
t
)
=
a
o
2
+
∑
n
=
1
∞
(
a
n
cos
nt
+
b
n
sin
nt
)
a
n
=
1
π
∫
-
π
π
f
(
t
)
cos
nt
·
ⅆ
t
(
n
=
1
,
2
,
3
…
)
b
n
=
1
π
∫
-
π
π
f
(
t
)
sin
nt
·
ⅆ
t
(
n
=
1
,
2
,
3
…
)
a
o
2
=
mVi
+
nVj
m
+
n
(
1
)
The first term of the function f(t) represents a DC component shown as an average voltage and the second term thereof represents a periodic component. If the periodic component of the function f(t) can be removed somehow, a pixel electrode which receives an oscillating voltage as shown in
FIG. 23
from a driver has an effect substantially equivalent to that the pixel electrode may have when it receives only a DC component represented by the first term of the function f(t).
If the route extending from a data line to a pixel electrode via a TFT is considered as a load of a driver, the route has characteristics as a low-pass filter determined based on a resistance component and a capacitance component existing on the route. If the frequency of the oscillating voltage is set sufficiently higher than a cut-off frequency determined by the characteristics as the low-pass filter, the value of the second term of the function f(t) can be sufficiently suppressed. As a result, a DC voltage shown as an average voltage is applied to the pixel electrode. Thus, in the oscillating voltage technique, a periodic component of an oscillating voltage output to a data line is suppressed using the characteristics of the route extending from the data line to the pixel electrode as the low-pass filter, so that only the DC component of the oscillating voltage is applied to the pixel electrode.
FIG. 24A
shows a configuration of a circuit which corresponds to one output of a 6-bit digital driver accor
Etoh Sunao
Okada Hisao
Frenel Vanel
Nixon & Vanderhye P.C.
Shalwala Bipin
Sharp Kabushiki Kaisha
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