Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-10-14
2003-02-04
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000
Reexamination Certificate
active
06515642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates for a driving circuit for a liquid crystal display, and more particularly, to a dynamic controller located in a driving circuit for a liquid crystal display to stabilize the supply voltage.
2. Description of Prior Art
For a small-scale liquid crystal display of a liquid crystal device such as a watch, a timer and a meter, a plurality of common signals in the horizontal axis are inter-connected with a plurality of segment signals in the vertical axis. The voltage levels of the common signals and the segment signals are each divided into several predetermined voltage levels, such as Vdd, VL
1
, VL
2
and VL
3
, as shown in FIG.
1
. Taking the example of the voltage levels of Vdd, VL
1
, VL
2
and VL
3
, Vdd is a voltage pair of VL
2
. Likewise, VL
1
is a voltage pair of VL
3
. By the operation of opening or closing several analog switches in
FIG. 1
, corresponding liquid crystal cells of the liquid crystal display will be respectively polarized or not polarized by changing the parasitic capacitors in the liquid crystal display. In the upper portion of
FIG. 1
, the upper input voltage level of the parasitic capacitor is controller by the common signals via the analog switches, and, in the lower portion of
FIG. 1
, the input voltage of the parasitic capacitor is controller by the segment signals via the analog switches. A frame frequency, shown in
FIG. 2
, is constructed by a negative cycle where the valid input voltage levels of the segment signals are all negative and by a positive cycle where the valid input voltage levels of the segment signals are all positive. The common signals can be regarded as being scanned in a manner as follows. In the negative cycle of the frame frequency, the common signals are switched between Vdd and VL
2
, and in the positive cycle of the frame frequency, the common signals are switched between VL
1
and VL
3
. In the negative cycle, the common signal with the voltage level Vdd means that the common signal is being scanned. In the positive cycle, the common signal with the voltage level VL
3
means that the common signal is being scanned. The voltage difference between the common signal and the segment signal at the moment will determine the voltage difference of the liquid crystal cell. As shown in
FIG. 2
, there are four common signals, and hence each portion of the negative and positive cycle of the frame frequency is divided into four pieces. In each divided cycle of the negative cycle, if the segment signal of the scanned common signal is VL
3
, since the voltage difference between the common signal and the segment signal is large, the liquid crystal cell will be turned on. In the same manner, in each divided cycle of the positive cycle, if the segment signal of the scanned common signal is Vdd, since the voltage difference between the common signal and the segment signal is large, the liquid crystal cell will be turned on. Otherwise, the liquid crystal cell will be turned off By multiplexing the liquid crystal cell to different voltage levels, the varied levels will cause the problem of floating the input voltage of the liquid crystal cell. The conventional solution for solving this problem is to provide a capacitor connected between the corresponding input level and the ground, as shown in
FIG. 3
, for achieving the goal of raising the voltage level and further stabilizing the voltage level. However, the installation of the capacitors will result in the problems of having too many pins for the integrated circuit, the area need for the integral layout being too large, and causing the trouble for preparing the capacitors. Another conventional solution for the varied voltage level is to construct a divided circuit by setting a plurality of resistors. As shown in
FIG. 4
, a plurality of resistors are biased between the drain supply voltage, Vdd, and the source supply voltage. Each interconnection point between two conjunct resistors derives an individual voltage level. The driving voltage level of the liquid crystal display is combined by these derived voltage levels and the drain supply voltage level. This conventional driving circuit has the drawback of consuming a large current, and of the area driven by the driving circuit being limited, for example, 10 &mgr;A to drive the area of 5 cm×2 cm of the liquid crystal display.
SUMMARY OF THE INVENTION
The object according to this invention is to overcome the drawbacks of the two conventional driving circuits for the liquid crystal display by constructing a plurality of dynamic controllers in a driving circuit for a liquid crystal display. The dynamic controller according to this invention is able to eliminate the necessity of the installation of the external capacitors for the conventional driving circuit and significantly reducing the driving current for the driving circuit. Also, the dynamic controller can drive a much larger area for a liquid crystal panel. The power saving function according to this invention is achieved by timely emitting the power-on signal once at the moment before and after each of the common signals is to be scanned so as to properly enable the Schmitt comparator.
Each dynamic controller of the driving circuit for the liquid crystal display in this invention is to keep the input voltage level steady in such a manner that when the output voltage of the dynamic controller is too large, the sink current in the dynamic controller will lower the output voltage level, and when the output voltage of the dynamic controller is too small, the Schmitt comparator in the dynamic controller will raise the output voltage level.
REFERENCES:
patent: 5869999 (1999-02-01), Mawet
patent: 6008669 (1999-12-01), Gerner
patent: 6057819 (2000-05-01), Sone et al.
patent: 6118415 (2000-09-01), Olson
patent: 6124843 (2000-09-01), Kodama
patent: 6201517 (2001-03-01), Sato
Patel Nitin
Samuels Gauthier & Stevens
Seiko Epson Corporation
Shankar Vijay
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