Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-03-01
2001-10-23
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S478000
Reexamination Certificate
active
06307407
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a charging pump booster circuit for supplying a voltage different from the source voltage and a driving circuit used for said booster circuit.
BACKGROUND OF THE INVENTION
A booster circuit is widely utilized for a circuit that requires a voltage level different from the source voltage, for example, a voltage higher than the source voltage or a negative voltage. An ordinary charging pump-type booster circuit has several boosting stages configured with rectifier elements, such as diodes and capacitors, depending on the required boosted voltage.
FIG. 2
is a circuit diagram showing an example of the configuration of a popular booster circuit. As shown in the figure, said booster circuit is configured with a booster control circuit
10
comprising driving circuits CH
1
and CH
2
, several diodes D
1
, D
2
, . . . , D
7
, and capacitors C
1
, C
2
, . . . , C
7
.
A switching signal SW, as a clock signal having a fixed frequency, is input into the input terminal of the booster control circuit
10
. In the booster control circuit
10
, the driving circuits CH
1
and CH
2
hold their respective output terminals T
1
and T
2
alternately to a high or a low level based on the switching signals SW input.
The diodes D
1
, D
2
, . . . , D
7
are connected in series between the feed line of a source voltage V
cc
and the output terminal T
B
of the booster circuit. Terminals of the capacitors C
1
, C
2
, . . . , C
6
are connected on one end to the midpoints ND
1
, ND
2
, . . . , ND
6
between the diodes D
1
, D
2
, . . . , D
7
, and the other ends are connected alternately to the output terminals T
1
and T
2
of the booster circuit
10
. The capacitor C
7
is connected between the output terminal T
B
of the booster circuit and the ground potential GND. Also, m quantity of Zener diodes ZD
1
, . . . , ZDm are series-connected in parallel with the capacitor C
7
. Furthermore, the number m of the quantity of Zener diodes is set based on the value of the desired boosted voltage V
B
.
When the booster circuit shown in
FIG. 2
is at work, the booster circuit
10
outputs the control signal from the output terminals T
1
and T
2
to be held at the high level and the low level alternately by the driving circuits CH
1
and CH
2
based on the switching signals SW input. For example, when the output terminal T
1
is at the high level and the output terminal T
2
is at the low level, potentials at the nodes ND
1
, ND
3
, and ND
5
are raised due to the capacitive coupling of the capacitors C
1
, C
3
, and C
5
, and as a result, the capacitors C
2
, C
4
, and C
6
get charged. On the other hand, when the output terminal T
1
is at the low level and the output terminal T
2
is at the high level, potentials at the nodes ND
2
, ND
4
, and ND
6
are raised due to the capacitive coupling of the capacitors C
2
, C
4
, and C
6
, and as a result, the capacitors C
3
, C
5
, and C
7
get charged. Furthermore, at this time, the capacitor C
1
connected to the anode side of the diode D
1
gets charged by the source voltage V
cc
to a voltage lower than the source voltage V
cc
by the amount equivalent to the voltage drop in the forward direction of the diode D
1
.
As described above, the capacitors at the respective boosting stages charge/discharge in turn based on the control signal from the booster circuit
10
, whereby the source voltage V
cc
and the boosted voltage V
B
corresponding to the number of the boosting stages are output from the output terminal of the booster circuit
10
. In the case of the booster circuit shown in
FIG. 2
, while a boosted voltage V
B
higher than the source voltage V
cc
can be output, a negatively boosted voltage can also be generated by changing the direction of the diodes D
1
, D
2
, . . . , D
7
.
FIG. 3
is a circuit diagram showing an example of the configuration of the driving circuits CH
1
and CH
2
constituting the booster control circuit
10
. As shown in the figure, driving circuits CHi (i=1, 2) are configured with resistance elements R
1
and R
2
, a pnp transistor Q
1
, and npn transistors Q
2
, Q
3
, and Q
4
. Bases of the transistors Q
3
and Q
4
are both connected to an input terminal T
in
, the collector of the transistor Q
3
is connected to the feed line of the source voltage V
cc
via the resistance element R
1
, and its emitter is grounded. Similarly, the collector of the transistor Q
4
is connected to the feed line of the source voltage V
cc
via the resistance element R
2
, and its emitter is grounded.
Base of the transistor Q
1
is connected to the collector of the transistor Q
4
, and its emitter is connected to the feed line of the source voltage V
cc
. Base of the transistor Q
2
is connected to the collector of the transistor Q
3
, and its emitter is grounded. Furthermore, collectors of the transistors Q
1
and Q
2
are connected to each other, and the junction point is connected to an output terminal T
out
.
Moreover, when the driving circuits CH
1
and CH
2
, shown in
FIG. 3
, are used to configure the booster circuit
10
shown in
FIG. 2
, the 2 driving circuits CH
1
and CH
2
are connected in series, input terminal T
in
of the driving circuit CH
1
of the former stage is connected to the input terminal for the switching signal SW, and input terminal T
in
of the driving circuit CH
2
of the latter stage is connected to the output terminal T
out
of the driving circuit of the former stage. Furthermore, output terminal of the driving circuit CH
1
of the former stage constitutes the output terminal T
1
shown in
FIG. 2
, and output terminal of the driving circuit CH
2
of the latter stage constitutes the output terminal T
2
shown in FIG.
2
.
In the driving circuits CH
1
and CH
2
shown in
FIG. 3
, level of the signal from the output terminal T
out
is controlled based on the signal input into input terminal T
in
. For example, when a high-level signal is input into the input terminal T
in
, the transistors Q
3
and Q
4
are turned on, and the collectors of these transistors are held to the low level. Accordingly, the transistor Q
1
is turned on, the transistor Q
2
is turned off, and the output terminal T
out
is held to the high level. Also, a charge current I
out
is output from said output terminal T
out
. To the contrary, when the input terminal T
in
is held to the low level, the transistors Q
3
and Q
4
are turned off, and the collectors of these transistors are both held to the high level. Accordingly, the transistor Q
1
is turned off, and the transistor Q
2
is turned on, so that the output terminal T
out
is held to the low level, and a drop current, that is, a discharge current which flows from the output terminal T
out
into the ground side via the transistor Q
2
is also supplied.
In the booster control circuit configured with the 2-stage driving circuits CH
1
and CH
2
connected in series in said manner, the output terminals T
1
and T
2
are held to the high level and the low level alternately based on the switching signals SW input, and the capacitors C
1
through C
6
of the respective boosting stages shown in
FIG. 2
accordingly get charged and discharged repeatedly. As a result, the boosted voltage V
B
higher than the source voltage V
cc
is output.
Incidentally, in the case of said conventional booster circuit, when an analog integrated circuit having so-called planer structure, in which circuit elements are formed on a plane of a semiconductor substrate, is used, the circuit element, in particular the transistors, may be difficult to form and still attain desired characteristics. For example, when the pnp transistor Q
1
shown in
FIG. 3
is formed by means of a lateral structure, a parasitic capacitance is added between the base and the substrate due to the nature of said configuration. As a result, because the frequency (f
T
transition frequency) at which the current amplification rate &bgr; of the transistors becomes 1 decreases, that is, high-frequency characteristics of the transistor deteriorate, when the switching operation is carried out t
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Zweizig Jeffrey
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