Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-08-30
2003-07-29
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S050000, C345S055000, C345S087000, C345S092000
Reexamination Certificate
active
06600483
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit used suitably for driving a capacitive load such as liquid crystal panel.
With respect to liquid crystal panel used in portable telephone or hand-held computer, a tendency of upsizing the same is promoted simultaneously with that of reduction in electric power consumption of the same year by year. In this respect, an equivalent capacity of a liquid crystal panel to be covered by a single driving circuit corresponds to a total capacity of a plurality of liquid crystal cells on a single common line or a single segment line. Such equivalent capacity depends upon an area of its panel, so that a value thereof reaches several thousand pF to several ten thousand pF, besides upsizing of liquid crystal panel advances year after year, and thus the equivalent capacity increases much more.
First of all, a first conventional example will be described hereunder.
FIG. 12
is a circuit diagram showing an archaic conventional driving circuit
100
which is arranged in such that the maximum value of a load to be driven is predetermined, whereby an operating current has been set in its design stage wherein reference characters MP
101
to MP
105
designate PMOS transistors, and MN
101
to MN
103
NMOS transistors, respectively. It is to be noted that a back gate of a PMOS transistor is connected to a high potential power source VDD, while a back gate of an NMOS transistor is connected to a low potential power source VSS, although such arrangement is not specifically explained hereinafter.
Reference numeral
101
designates a differential amplifying circuit composed of MP
101
, MP
102
, MP
104
, MN
101
, and MN
102
,
102
a noninverting input terminal,
103
an inverting input terminal,
104
an output circuit composed of MN
103
, MP
105
, and a phase compensating capacitor C
102
,
105
an output terminal, and C
101
a capacitive load, respectively. In this arrangement, MP
104
,and MP
105
are connected to MP
103
in a current mirror fashion, so that a bias current corresponding to a current source I
101
flows through them.
FIG. 13
is a waveform diagram of voltages and electric currents in respective sections of the driving circuit
100
wherein the inverting input terminal
103
is commonly connected to the output terminal
105
to operate the whole arrangement as a voltage follower. In the case shown in
FIG. 13
, VDD=0 V, VSS=−10 V, the capacitive load C
101
is 10,000 pF, and a driving signal Vin (200 &mgr;s cycle, and 50% duty(duty ratio)) is fed to the noninverting input terminal
102
. In the figure, time is plotted as abscissa and drain voltage Vd(#) of a transistor #, drain current Id(#) of the transistor #, and current consumption Ivdd flowing through the power source VDD as ordinates, respectively.
A comparatively large current consumption Ivdd is observed for a comparatively long period of time from the time at which the driving signal Vin at the input terminal
102
varies. At least 258.26 &mgr;A was required for the current Ivdd heretofore. Furthermore, the driving circuit
100
is arranged in such that the current of I
101
and each size ratio of MP
104
and MP
105
with respect to MP
103
have been previously determined in response to the possible maximum capacity of the capacitive load C
101
, whereby a bias current flowing through MP
104
and MP
105
is decided. In this respect, however, since such bias current flows in even a steady state wherein the driving signal Vin does not vary, there is such a problem that the bias current (idling current) is useless, so that its driving efficiency decreases in the case where a small load is driven.
A second conventional example will be described.
FIG. 14
is a circuit diagram showing a driving circuit
120
which is obtained by improving the driving circuit
100
shown in
FIG. 12
in such that an operating current is increased tentatively for only a timing period where a driving signal Vin varies and which has been proposed by Japanese Unexamined Patent Publication No. 221560/1995. In
FIG. 14
, reference characters MP
121
through MP
125
designate PMOS transistors, while MN
121
through MN
124
NMOS transistors, respectively.
Reference character
121
denotes a differential amplifying circuit composed of MP
121
, MP
122
, MP
124
, MN
121
, and MN
122
,
122
a noninverting input terminal,
123
an inverting input terminal,
124
an output circuit composed of MN
123
, MP
125
, and a phase compensating capacitor C
122
,
125
an output terminal, and C
121
a capacitive load, respectively. MP
124
and MP
125
are connected to MP
123
in a current mirror fashion. MN
124
, and resistors R
121
and R
122
constitute a bias switching circuit
126
. Reference numeral
127
designates a control terminal.
In the driving circuit
120
shown in
FIG. 14
, the inverting input terminal
123
is commonly connected with the output terminal
125
, so that the whole arrangement operates as a voltage follower. In the arrangement, a voltage with “Hi” level is applied to the control terminal
127
in exact timing with a transition of the driving signal Vin by its corresponding term to bring MN
124
into conduction, so that R
122
is short-circuited, whereby an operating current flowing through MP
124
and MP
125
is increased to supply a driving current requested by the capacitive load C
121
. Accordingly, an operating current in the case where it is not required for driving operation decreases and its driving efficiency is remarkably improved as compared with the driving circuit
100
shown in FIG.
12
.
However, although the driving circuit
120
can cope with a load which has been predetermined beforehand, its operating current can be switched only in two stages, so that there is such a problem that a driving force becomes insufficient with respect to a larger load than that forecasted, and on the contrary, a useless current flows with respect to a smaller load than that which has been forecasted. Moreover, when a frequency of a driving pulse becomes high, a rate of time occupied by a term wherein a current is allowed to increase builds up also so that an effect for saving electric current decreases. In addition, since electric current available efficiency itself for a driving period of time is not different from that of the circuit shown in
FIG. 12
, an electric current increases when its load capacity increases.
A third conventional example will be described.
FIG. 15
is a circuit diagram showing a driving circuit
140
wherein a voltage change in a differential circuit is converted into current change to increase its output driving force. The driving circuit
140
is called also by the name of “transconductance amplifier” and which is known from long ago. In
FIG. 15
, reference characters MP
141
to MP
146
designate PMOS transistors, and MN
141
to MN
144
NMOS transistors, respectively.
Reference numeral
141
denotes a differential amplifying circuit composed of MP
141
, MP
142
, MP
145
, MN
141
, and MN
142
,
142
a noninverting input terminal,
143
an inverting input terminal,
144
an output circuit composed of MP
146
and MN
143
,
145
an output terminal, and C
141
a capacitive load, respectively. MN
144
and MP
144
are served for supplying a drain voltage change in MN
141
to MP
146
. To MN
143
is supplied a drain voltage in MN
142
. A bias current corresponding to an electric current of a current source I
141
is flowing through MP
145
by means of MP
143
.
FIG. 16
is a waveform diagram of voltages and electric currents in respective sections of the driving circuit
140
wherein the inverting input terminal
143
is commonly connected with the output terminal
145
to operate the whole arrangement as a voltage follower. In the case shown in
FIG. 16
, VDD=0 V, VSS=−10 V, the capacitive load C
141
is 10,000 pF and a driving signal Vin (200 &mgr;s cycle, and 50% duty) is fed to the noninverting input terminal
142
. In the figure, time is plotted as abscissa and drain voltage Vd(#) of a t
Akita Shinichi
Kawano Tomoyuki
New Japan Radio Co. Ltd.
Shalwala Bipin
Shapiro Leonid
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