Driving circuit

Details Driving circuit Driving circuit

1999-12-10

2002-02-05

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S079000, C341S079000

Reexamination Certificate

active

06344814

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a driving circuit for outputting a driving voltage and, more particularly, to a driving circuit that outputs voltages in alternating driving voltage ranges.
2. Description of the Related Art
A conventional liquid crystal display (LCD) comprises an array of pixels arranged in rows and columns. The image information displayed at each pixel, e.g., a shade of grey or color, is controlled by the magnitude of a driving voltage applied thereto. The LCD is typically driven by enabling one row of pixels of the display, at one time, and applying driving voltages to the respective columns of pixels. This process is repeated for each row of the display to generate a complete displayed image. The entire process is periodically repeated to updated the displayed image.
In accordance with current designs of LCDs, it is desirable to apply a driving voltage to each pixel in a relatively large voltage range, e.g., 0-12 volts. Theoretically, in order for a driving circuit constructed of MOSFETs to be capable of outputting driving voltages over such a range, the individual transistors would need to be designed to tolerate the highest output voltage, e.g., 12 volts. This would result in the transistors each being relatively physically large to provide tolerance to an output voltage that the transistors are only occasionally subjected to during operation. Also, disadvantageously, the larger size of these transistors results in the circuitry into which they are integrated to take up more physical space. Such additional physical space generally equates with additional cost and size for the LCD driving circuit.
One solution to the problems created by the use of MOSFETs sized to tolerate the full range of driving voltage is to limit the range of voltage to which each individual transistor in the driving circuit is subjected. One way this has been accomplished is by limiting the voltages applied across the gate oxides of the driving transistors to be less than a gate oxide breakdown voltage. More particularly, this is achieved for each driving transistor by selecting a fixed voltage for application to its gate terminal to result in the voltage across the gate oxide being less than the gate oxide breakdown voltage. However, in order to implement this arrangement in a driving circuit with a large output voltage range, it is necessary to divide the desired driving voltage range into at least two portions and provide at least two MOSFETs respectively associated with the two portions.
It is desirable in some LCD applications to apply to individual pixels a driving voltage that alternates between voltages respectively having magnitudes in upper and lower voltage ranges. This alternation of voltage magnitude is carried out in order to achieve an improved displayed image quality. The alternating voltage magnitudes can be applied to pixels such that in each display cycle any two adjacent pixels in a row respectively have applied to them voltages in the upper and lower voltage ranges. The voltages can also be applied such that in each display cycle any two pixels in both the row and column directions respectively have applied thereto the voltages in the upper and lower voltage ranges.
In conventional practice it has been necessary to couple the desired driving voltages to each pixel through multiplexer circuitry. Such multiplexer circuitry undesirably increases circuit complexity and slows down LCD operation. Further, the conventional practice of providing a multiplexer to alternately select the outputs of a pair of digital-to-analog converters (DACs) outputting voltages in the upper and lower voltage ranges for application to a pair of LCD columns results in unequal signal path routing lengths between the DACs and the LCD columns, which further limits the operating speed of the LCD driving circuit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a driving circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the method and apparatus particularly pointed out in the written description and claims hereof as well as the appended drawings. To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, the invention is directed to a driving circuit for outputting driving signals from an array of digital-to-analog converters to an array of output terminals. The driving circuit comprises first and second output terminals; a first digital-to-analog converter (DAC) for outputting analog voltages in a first voltage range; a second DAC for outputting analog voltages in a second voltage range; and a third DAC for outputting analog voltages in the second voltage range. The first and second output terminals are coupled to receive a first analog voltage from the first DAC and a second analog voltage from the second DAC, respectively, during a first time cycle, and the first and second output terminals are coupled to receive a third analog voltage from the third DAC and a fourth analog voltage from the first DAC, respectively, during a second time cycle.
Also in accordance with the present invention there is provided a method for outputting an array of alternating high-range and low-range driving signals from an array of digital-to-analog converters (DACs) to an array of output terminals including at least first and second output terminals. The method comprises: defining successive alternating first and second time cycles; outputting, during the first time cycle, a first analog voltage in a first voltage range from a first DAC of the array of DACs to the first output terminal; outputting, during the first time cycle, a second analog voltage in a second voltage range from a second DAC of the array of DACs to the second output terminal; outputting, during the second time cycle, a third analog voltage in the second range from a third DAC of the array of DACs to the first output terminal; and outputting, during the second time cycle, a fourth analog voltage in the first range from the first DAC to the second output terminal.
Further in accordance with the present invention there is provided a digital-to-analog converter for converting into an analog output a digital input value, comprising: a decoder for receiving the digital input value and providing decoded bits; first and second sets of logic gates respectively coupled to receive the decoded bits on a first input; a first set of output transistors each having a conductive state controlled by an output of a corresponding one of the first set of logic gates; a second set of output transistors each having a conductive state controlled by an output of a corresponding one of the second set of logic gates; an inverter coupled to receive an externally applied binary signal on its input and provide an inversion of the binary signal on its output; the first set of logic gates coupled to receive the output of the inverter on a second input; the second set of logic gates coupled to receive the binary signal on a second input; an array of analog voltage nodes; a first output terminal; a second output terminal; the first set of output transistors each coupled between the first output terminal and predetermined points along said array of analog voltage nodes; the second set of output transistors each coupled between the second output terminal and the predetermined points along said array of analog voltage nodes; a first shunting transistor coupled between a first node for receiving a first power supply voltage and the first output terminal and having a conductive state controlled by the inverter output; and a second shunting transistor coupled between the first

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