Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-06-28
2004-02-03
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S212000, C345S213000, C345S060000, C345S062000, C315S169400
Reexamination Certificate
active
06686912
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to driving apparatus and methods, plasma display apparatus, and power supply circuits for plasma display panel, suitable for, e.g., AC-driven plasma displays.
2. Description of the Related Art
In recent years, demand has increased for replacing CRTs with flat matrix type display apparatus such as PDPs (Plasma Display Panels), LCDs (Liquid Crystal Displays), and ELDs (Electro-Luminescence Displays) in terms of decreased thickness. In particular, AC-driven PDPs are excellent in visibility because they are self-emission type displays. They can make display on a large screen with a thin device. Thus they have received a great deal of attention as a next-generation display that can realize higher image quality than CRTs.
Conventionally well-known AC-driven PDPs are classified into two-electrode type PDPs performing selective discharge (address discharge) and sustain discharge with two electrodes, and three-electrode type PDPS performing address discharge further using a third electrode. The three-electrode type PDPs are further classified into PDPs having its third electrode formed on the same substrate as its first and second electrodes, and PDPs having its third electrode formed on another substrate opposite to the substrate of its first and second electrodes.
All types of PDP apparatus described above are based on the same principle. Thus the construction of a PDP apparatus will be described below wherein first and second electrodes for performing sustain discharge are formed on a first substrate, and a third electrode is separately prepared on a second substrate opposite to the first substrate.
FIG. 1
is a diagrammatic view showing the whole construction of an AC-driven PDP apparatus. Referring to
FIG. 1
, an AC-driven PDP
1
is provided with parallel scanning electrodes Y
1
to Yn and common electrodes X formed on one surface, and address electrodes A
1
to Am formed on the opposite surface so as to be perpendicular to the electrodes Y
1
to Yn and X. Each common electrode X is disposed close to its corresponding one of the scanning electrodes Y
1
to Yn. The common electrodes X are commonly connected to one terminal.
The common terminal of the common electrodes X is connected to the output terminal of an X-side circuit
2
. The scanning electrodes Y
1
to Yn are connected to the output terminals of a Y-side circuit
3
. The address electrodes A
1
to Am are connected to the output terminals of an address-side circuit
4
. The X-side circuit
2
comprises a circuit for repeating a discharge. The Y-side circuit
3
comprises a circuit for line-sequential scan, and a circuit for repeating a discharge. The address-side circuit
4
comprises a circuit for selecting a line to be displayed. These X-side circuit
2
, Y-side circuit
3
, and address-side circuit
4
are controlled with control signals from a control circuit
5
. More specifically, the address-side circuit
4
and the circuit for line-sequential scan in the Y-side circuit determine cells to be lit, and the display of the PDP is made by repeating discharges of the X- and Y-side circuits
2
and
3
.
The control circuit
5
generates the control signals on the basis of external display data D, a clock CLK representing read timing for the display data D, a horizontal sync signal HS, and a vertical sync signal VS, and supplies the control signals to the X-side circuit
2
, the Y-side circuit
3
, and the address-side circuit
4
.
FIG. 2A
is a sectional view of a cell Cij as one pixel, which is in the i-th row and the j-th column. Referring to
FIG. 2A
, a common electrode X and a scanning electrode Yi are formed on a front glass substrate
11
. The structure is coated with a dielectric layer
12
for insulating the electrodes from a discharge space
17
. The resultant structure is further coated with an MgO (magnesium oxide) protective film
13
.
An address electrode Aj is formed on a back glass substrate
14
opposite to the front glass substrate
11
. A dielectric layer
15
is formed on the address electrode Aj. The dielectric layer
15
is coated with a fluorescent substance. The discharge space
17
between the MgO protective film
13
and the dielectric layer
15
is charged with Ne+Xe Penning gas.
FIG. 2B
is for explaining a capacitance Cp in the AC-driven PDP. Referring to
FIG. 2B
, in the AC-driven PDP, capacitance components Ca, Cb, Cc appear in the discharge space
17
, between the common and scanning electrodes X and Y, and within the front glass substrate
11
, respectively. The sum of them gives the capacitance Cpcell per cell (Cpcell=Ca+Cb+Cc). The total of the capacitances Cpcell of all cells gives the panel capacitance Cp.
FIG. 2C
is for explaining fluorescence in the AC-driven PDP. Referring to
FIG. 2C
, fluorescent substances for red, blue, and yellow are applied to be arranged each color in stripes on the inside surfaces of a ribs
16
. A discharge between common and scanning electrodes X and Y excites the corresponding fluorescent substance
18
to fluoresce.
FIG. 3
is a timing chart showing voltage waveforms in a driving method of the AC-driven PDP.
FIG. 3
shows one of subfields making up one frame. One subfield is divided into a reset period consisting of a full write period and a full erase period, an address period, and a sustain discharge period.
First in the reset period, all the scanning electrodes Y
1
to Yn are set at the ground level (0 V). Simultaneously with this, a full write pulse having a voltage Vs+Vw (about 400 V) is applied to the common electrodes X. At this time, all the address electrodes A
1
to Am are at a potential Vaw (about 100 V). As a result, discharge occurs in every cell of every display line to generate wall charges, independently of the preceding display state.
Next, the potentials of the common electrodes X and the address electrodes A
1
to Am become 0 V. The voltage by wall charges themselves then exceeds the discharge start voltage in every cell, and discharge starts. This discharge makes no wall charge because there is no difference in potential between electrodes. Space charges are neutralized by themselves to end discharge. This is so-called self-erase discharge. By this self-erase discharge, all cells in the panel become a uniform state free from wall charges. This reset period serves to set all cells in the same state independently of the ON/OFF state of each cell in the preceding subfield. This makes it possible to perform the subsequent address (write) discharge stably.
Next, in the address period, address discharge is line-sequentially performed to turn each cell ON/OFF in accordance with display data. More specifically, a voltage at −Vy level (about −150 V) is applied to the scanning electrode Y
1
corresponding to the first display line, and a voltage at −Vsc level (about −50 V) is applied to the scanning electrodes Y
2
to Yn corresponding to the remaining display lines. At the same time, an address pulse having a voltage Va (about 50 V) is selectively applied to an address electrode Aj corresponding to a cell to undergo sustain discharge, i.e., to be turned ON, in the address electrodes A
1
to Am.
Consequently, discharge occurs between the scanning electrode Y
1
and the address electrode Aj of the cell to be turned ON. With this priming (pilot), discharge between the scanning electrode Y
1
and the corresponding common electrode X having a voltage Vx starts immediately. An amount of wall charges enough for the next sustain discharge is then stored on the surface of the MgO protective film
13
on the common electrode X and the scanning electrode Y
1
of the selected cell. Similarly for the scanning electrodes Y
2
to Yn corresponding to the remaining display lines, the voltage at −Vy level is applied to the scanning electrodes of selected cells in order, and the voltage at −Vsc level is applied to the remaining scanning electrodes of non-selected cells. New display data is thereby written in all d
Kishi Tomokatsu
Sakamoto Tetsuya
Tomio Shigetoshi
Shalwala Bipin
Sheng Tommy
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