Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-07-03
2007-07-03
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S204000, C345S211000
Reexamination Certificate
active
10805422
ABSTRACT:
A source driver includes a hold memory circuit and a switch circuit. The hold memory circuit includes (i) delay circuits for delaying an inputted horizontal synchronization signal, (ii) hold latch cells each for latching display data in accordance with the horizontal synchronization signal that has been delayed by the delay circuit, and (iii) a control circuit for outputting a display start signal to the switch circuit upon receipt of the horizontal synchronization signal that has been delayed by the delay circuit. The switch circuit outputs a plurality of driving signals in accordance with the display start signal. This allows the peak value of the power source current to be reduced, and enables to avoid the malfunction of the source driver due to the misidentification of the horizontal synchronization signal and to avoid that the output timing becomes nonuniform.
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Harness & Dickey & Pierce P.L.C.
Hjerpe Richard
Sharp Kabushiki Kaisha
Tran My-Chau T.
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